Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for c4c0d10a58e723f797874d1dd70151ecd6342814 Apr 26 - Mar 24
- Total: 439 commits
- Average per day: 0.6 commits
- Authors: 3
Commits per day of month
Commits per weekday
Commits per day hour (UTC)