Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for c49619fdcd7814394584d51ea7506b21b251f2e1 Apr 26 - Apr 11
- Total: 777 commits
- Average per day: 0.4 commits
- Authors: 5
Commits per day of month
Commits per weekday
Commits per day hour (UTC)