Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for ae549ed413b3d55ebac0d2b29fd9aaf04ce6c8a7 Apr 26 - Oct 16

  • Total: 382 commits
  • Average per day: 0.7 commits
  • Authors: 3

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