Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for aabad99e4758c8df6bb02623f8ff4814367022a8 Apr 26 - Mar 15

  • Total: 130 commits
  • Average per day: 0.4 commits
  • Authors: 1

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