Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 901e1d6a9d1550dd2895a2a74c4f7957864bf39e Apr 26 - Mar 29

  • Total: 458 commits
  • Average per day: 0.7 commits
  • Authors: 3

Commits per day of month

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