Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 896e116ae03ba9b73a447977bbf2b26a93982a22 Apr 26 - Jun 08

  • Total: 43 commits
  • Average per day: 1.0 commits
  • Authors: 1

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