Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 8757841e72b4bc4d96315616b18a4c3a47c9ecd8 Apr 26 - Sep 16

  • Total: 346 commits
  • Average per day: 0.7 commits
  • Authors: 2

Commits per day of month

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