Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 715779369b3f357bf5e23eba6d1bb25e0008af7e Apr 26 - Dec 04

  • Total: 688 commits
  • Average per day: 0.7 commits
  • Authors: 5

Commits per day of month

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