Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 63e3b7c0ae869ae3a18b94376504445204d8fd98 Apr 26 - Apr 26

  • Total: 4 commits
  • Average per day: 4.0 commits
  • Authors: 1

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