Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for 608bcbd9024b58d252e585d603437c52ec0ca74b Apr 26 - Sep 07
- Total: 335 commits
- Average per day: 0.7 commits
- Authors: 2
Commits per day of month
Commits per weekday
Commits per day hour (UTC)