Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 56006910c67dc8423363f76c778424fb1714165c Apr 26 - Jan 26

  • Total: 70 commits
  • Average per day: 0.3 commits
  • Authors: 1

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