Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for 51c11c7e18a9846a1e4829d48535ff0c46dda4a5 Apr 26 - Apr 10
- Total: 773 commits
- Average per day: 0.4 commits
- Authors: 5
Commits per day of month
Commits per weekday
Commits per day hour (UTC)