Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 46f1a6c96d2ce388d387203928ac0de49717e63c Apr 26 - Dec 29

  • Total: 786 commits
  • Average per day: 0.6 commits
  • Authors: 5

Commits per day of month

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