Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 466a4a4e037e104fd297caba695f7e7f059d7c10 Apr 26 - Feb 10

  • Total: 90 commits
  • Average per day: 0.3 commits
  • Authors: 1

Commits per day of month

Commits per weekday

Commits per day hour (UTC)