Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 45d1f6b7acd81f50b4ba5dc450d366899bae09cc Apr 26 - Apr 09

  • Total: 155 commits
  • Average per day: 0.4 commits
  • Authors: 1

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