Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for 30fae557dfe04b985da087dad3946a0c2dd93861 Apr 26 - Oct 31
- Total: 396 commits
- Average per day: 0.7 commits
- Authors: 3
Commits per day of month
Commits per weekday
Commits per day hour (UTC)