Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 30417be405843c5378e529b6660ce73047bcf6d1 Apr 26 - Jul 14

  • Total: 586 commits
  • Average per day: 0.7 commits
  • Authors: 5

Commits per day of month

Commits per weekday

Commits per day hour (UTC)