Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 2ec40de813441a3f7d4bbca5b4b26895b0a734be Apr 26 - Jan 14

  • Total: 61 commits
  • Average per day: 0.2 commits
  • Authors: 1

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