Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 21e45a9976b1094e94d7c808c8ead12d63a7dce2 Apr 26 - Mar 05

  • Total: 119 commits
  • Average per day: 0.4 commits
  • Authors: 1

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