Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for 1de3d68f11ddc973f5116b9612809e05307f2ef0 Apr 26 - Aug 03
- Total: 287 commits
- Average per day: 0.6 commits
- Authors: 2
Commits per day of month
Commits per weekday
Commits per day hour (UTC)