Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 1d2f08b7fcdde69ae15ec38ee7e29ffc6747f49d Apr 26 - Apr 21

  • Total: 166 commits
  • Average per day: 0.5 commits
  • Authors: 1

Commits per day of month

Commits per weekday

Commits per day hour (UTC)