Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 1725c547020b478854be2eca7fa014650d2fb926 Apr 26 - Mar 21

  • Total: 746 commits
  • Average per day: 0.4 commits
  • Authors: 5

Commits per day of month

Commits per weekday

Commits per day hour (UTC)