Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 1182a36e4920f0924ea310a95b7e779131cf076e Apr 26 - Aug 15

  • Total: 298 commits
  • Average per day: 0.6 commits
  • Authors: 2

Commits per day of month

Commits per weekday

Commits per day hour (UTC)