Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 0be6290b3a1f73a5d0452399b826577b062c242b Apr 26 - Apr 19

  • Total: 785 commits
  • Average per day: 0.4 commits
  • Authors: 5

Commits per day of month

Commits per weekday

Commits per day hour (UTC)