Programming languages used in this repository

  •   Verilog
    56.25 %
  •   Python
    29.11 %
  •   HCL
    7.27 %
  •   SystemVerilog
    6.82 %
  •   Tcl
    0.3 %

Commit statistics for 07e41034fb710a28aa6919db6aee5d6ff707488c Apr 26 - Feb 16

  • Total: 731 commits
  • Average per day: 0.5 commits
  • Authors: 5

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