...
 
Commits (39)
......@@ -24,6 +24,8 @@ COMMAND_FILES = py393/hargs \
py393/hargs-after \
py393/hargs-eyesis \
py393/hargs-hispi \
py393/hargs-vospi \
py393/hargs-post-vospi \
py393/hargs-post-par12 \
py393/hargs-power_par12 \
py393/hargs-power-eyesis \
......
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......@@ -129,6 +129,8 @@ module cmprs_cmd_decode#(
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
parameter CMPRS_CBIT_ROWS_LSB = 28, // bit # Four height LSBs in raw mode
parameter CMPRS_CBIT_ROWS_LSB_BITS = 4, // number of bits to control four height LSBs in raw mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
......@@ -205,6 +207,7 @@ module cmprs_cmd_decode#(
output reg [ 2:0] cmprs_qpage, // [2:0] - quantizator page number (0..7)
output reg cmprs_dcsub, // subtract dc level before DCT, restore later
output reg [ 1:0] cmprs_fmode, //[1:0] - focus mode
output reg [ 3:0] raw_rows_lsb, // Four LSBs of the window height - used in raw mode
output reg [ 1:0] bayer_shift, // additional shift to bayer mosaic
output reg ignore_color,
......@@ -246,6 +249,7 @@ module cmprs_cmd_decode#(
reg cmprs_dcsub_mclk; // subtract dc level before DCT, restore later
reg [ 3:0] cmprs_mode_mclk; // [3:0] - compressor mode
reg [ 1:0] cmprs_fmode_mclk; //[1:0] - focus mode
reg [ 3:0] rows_lsb_mclk; // [3:0] - Four LSBs of the window height - used in raw mode
reg [ 1:0] bayer_shift_mclk; // additional shift to bayer mosaic
reg [30:0] format_mclk; // left margin and macroblock rows/columns
......@@ -256,6 +260,8 @@ module cmprs_cmd_decode#(
reg cmprs_dcsub_xclk; // subtract dc level before DCT, restore later
reg [ 3:0] cmprs_mode_xclk; // [3:0] - compressor mode
reg [ 1:0] cmprs_fmode_xclk; //[1:0] - focus mode
reg [ 3:0] rows_lsb_xclk; // Four LSBs of the window height - used in raw mode
reg [ 1:0] bayer_shift_xclk; // additional shift to bayer mosaic
reg [30:0] format_xclk; // left margin and macroblock rows/columns
......@@ -311,6 +317,9 @@ module cmprs_cmd_decode#(
if (mrst) cmprs_fmode_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FOCUS]) cmprs_fmode_mclk <= di_r[CMPRS_CBIT_FOCUS-1 -:CMPRS_CBIT_FOCUS_BITS];
if (mrst) rows_lsb_mclk <= 4'hf;
else if (ctrl_we_r && di_r[CMPRS_CBIT_ROWS_LSB]) rows_lsb_mclk <= di_r[CMPRS_CBIT_ROWS_LSB-1 -:CMPRS_CBIT_ROWS_LSB_BITS];
if (mrst) bayer_shift_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_BAYER]) bayer_shift_mclk <= di_r[CMPRS_CBIT_BAYER-1 -:CMPRS_CBIT_BAYER_BITS];
......@@ -343,6 +352,7 @@ module cmprs_cmd_decode#(
cmprs_dcsub_xclk <= cmprs_dcsub_mclk;
cmprs_mode_xclk <= cmprs_mode_mclk;
cmprs_fmode_xclk <= cmprs_fmode_mclk;
rows_lsb_xclk <= rows_lsb_mclk;
bayer_shift_xclk <= bayer_shift_mclk;
end
......@@ -356,6 +366,7 @@ module cmprs_cmd_decode#(
cmprs_qpage <= cmprs_qpage_xclk;
cmprs_dcsub <= cmprs_dcsub_xclk;
cmprs_fmode <= cmprs_fmode_xclk;
raw_rows_lsb <= rows_lsb_xclk;
bayer_shift <= bayer_shift_xclk;
left_marg <= format_xclk[CMPRS_FRMT_LMARG +: CMPRS_FRMT_LMARG_BITS];
......
......@@ -62,7 +62,8 @@ module cmprs_raw_buf_iface #(
input cmprs_run_mclk, // 0 - off or stopping, reset frame_pre_run
// input [ 4:0] left_marg, // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile)
input [12:0] n_blocks_in_row_m1, // number of macroblocks in a macroblock row minus 1
input [12:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1
// input [12:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1
input [16:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1
input stuffer_running, // @xclk, active while bit stuffer or trailer are running
input raw_be16, // 0: bytes 0-1-2-3-4-5..., 1: bytes 1-0-3-2-5-4...
output [11:0] buf_ra, // buffer read address (2 MSB - page number)
......@@ -206,7 +207,8 @@ module cmprs_raw_buf_iface #(
quad_last <= mode_valid && !(|quads_left); // valid from 2 after frame_pre_start_r or after quad_r[3]
if (frame_pre_start_r) rows_left <= {n_block_rows_m1, 4'b1111};
// if (frame_pre_start_r) rows_left <= {n_block_rows_m1, 4'b1111};
if (frame_pre_start_r) rows_left <= n_block_rows_m1; //n_block_rows_m1 now combines n_block_rows_m1 and tile vstep ?
else if ((quad_r[2] && quad_last)) rows_left <= rows_left - 1;
rows_last <= {rows_last[0], mode_valid & ~(|rows_left)};
......
......@@ -84,6 +84,9 @@ module compressor393 # (
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
parameter CMPRS_CBIT_ROWS_LSB = 28, // bit # Four height LSBs in raw mode
parameter CMPRS_CBIT_ROWS_LSB_BITS = 4, // number of bits to control four height LSBs in raw mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
......@@ -382,6 +385,8 @@ module compressor393 # (
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
.CMPRS_CBIT_FOCUS_BITS (CMPRS_CBIT_FOCUS_BITS),
.CMPRS_CBIT_ROWS_LSB (CMPRS_CBIT_ROWS_LSB),
.CMPRS_CBIT_ROWS_LSB_BITS (CMPRS_CBIT_ROWS_LSB_BITS),
.CMPRS_CBIT_RUN_RST (CMPRS_CBIT_RUN_RST),
.CMPRS_CBIT_RUN_STANDALONE (CMPRS_CBIT_RUN_STANDALONE),
.CMPRS_CBIT_RUN_ENABLE (CMPRS_CBIT_RUN_ENABLE),
......
......@@ -78,6 +78,8 @@ module jp_channel#(
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
parameter CMPRS_CBIT_ROWS_LSB = 28, // bit # Four height LSBs in raw mode
parameter CMPRS_CBIT_ROWS_LSB_BITS = 4, // number of bits to control four height LSBs in raw mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
......@@ -245,7 +247,7 @@ module jp_channel#(
wire jp4_dc_improved; // in JP4 mode, compare DC coefficients to the same color ones
// wire [ 1:0] tile_margin; // margins around 16x16 tiles (0/1/2)
// wire [ 2:0] tile_shift; // tile shift from top left corner
wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 7 - mono8 (not yet implemented)
wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 6 - raw, 7 - mono8 (not yet implemented)
wire scale_diff; // divide differences by 2 (to fit in 8-bit range)
wire hdr; // second green absolute, not difference
wire subtract_dc; // subtract/restore DC components
......@@ -253,7 +255,7 @@ module jp_channel#(
wire [CMPRS_CSAT_CR_BITS-1:0] m_cr; // [9:0] scale for CR - default 0.713 (10'hb6)
wire [ 1:0] cmprs_fmode; // focusing/overlay mode
wire [ 3:0] raw_rows_lsb; // four LSBs of window height in raw mode, 0 means 'h10, 'hf means f
//TODO: assign next 5 values from converter_type[2:0]
wire [ 5:0] mb_w_m1; // macroblock width minus 1
wire [ 5:0] mb_h_m1; // macroblock height -1
......@@ -701,6 +703,8 @@ module jp_channel#(
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
.CMPRS_CBIT_FOCUS_BITS (CMPRS_CBIT_FOCUS_BITS),
.CMPRS_CBIT_ROWS_LSB (CMPRS_CBIT_ROWS_LSB),
.CMPRS_CBIT_ROWS_LSB_BITS (CMPRS_CBIT_ROWS_LSB_BITS),
.CMPRS_CBIT_RUN_RST (CMPRS_CBIT_RUN_RST),
.CMPRS_CBIT_RUN_STANDALONE (CMPRS_CBIT_RUN_STANDALONE),
.CMPRS_CBIT_RUN_ENABLE (CMPRS_CBIT_RUN_ENABLE),
......@@ -760,7 +764,8 @@ module jp_channel#(
.cmprs_en_late_xclk (stuffer_en), // output reg - extended enable to allow stuffer to gracefully finish
.cmprs_qpage (cmprs_qpage), // output[2:0] reg
.cmprs_dcsub (subtract_dc), // output reg
.cmprs_fmode (cmprs_fmode), // output[1:0] reg
.cmprs_fmode (cmprs_fmode), // output[1:0] reg
.raw_rows_lsb (raw_rows_lsb), // output[3:0] reg
.bayer_shift (bayer_phase), // output[1:0] reg
.ignore_color (ignore_color), // output reg
.four_blocks (), // output reg Not used?
......@@ -888,7 +893,7 @@ module jp_channel#(
.frame_go (frame_go_raw), // input
.cmprs_run_mclk (cmprs_run_mclk), // input
.n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0]
.n_block_rows_m1 (n_block_rows_m1), // input[12:0]
.n_block_rows_m1 ({n_block_rows_m1,raw_rows_lsb}), // input[12:0]
.stuffer_running (stuffer_running), // input
.raw_be16 (raw_be16), // input
.buf_ra (raw_buf_ra), // output[11:0]
......
......@@ -35,10 +35,37 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, foxed bug, all met
// parameter FPGA_VERSION = 32'h03930110; //A serial - 17.4 - restored delay after linear, foxed bug, timing met
// parameter FPGA_VERSION = 32'h03930110; // serial - 17.4 - restored delay after linear, foxed bug, timing failed
// parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, foxed bug, all met
parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm
// parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode
// parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
// parameter FPGA_VERSION = 32'h03930135; // Adding multi-cam reset
// parameter FPGA_VERSION = 32'h0393014; // Adding multi-cam reset - buggy
// parameter FPGA_VERSION = 32'h03930133; // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0
// parameter FPGA_VERSION = 32'h03930132; // Sync from serial bumber start, added output (with hact)
// parameter FPGA_VERSION = 32'h03930131; // Sync from serial bumber start
// parameter FPGA_VERSION = 32'h03930130; // Adding output for receive start frame
// parameter FPGA_VERSION = 32'h0393012f; // debugging resync on othjer sesnor
// parameter FPGA_VERSION = 32'h0393012e; // re-arranged control bits, added telemetry on/off
// parameter FPGA_VERSION = 32'h0393012d; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012c; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012b; // debugging
// parameter FPGA_VERSION = 32'h0393012a; // debugging
// parameter FPGA_VERSION = 32'h03930129; // adding synchronization by discard packets
// parameter FPGA_VERSION = 32'h03930128; // output dbg_segment_stb on [7]
// parameter FPGA_VERSION = 32'h03930127; // output vsync_use, reduced sclk to 10MHz
// parameter FPGA_VERSION = 32'h03930126; // fast slew to sensor
// parameter FPGA_VERSION = 32'h03930125; // fast slew to sensor
// parameter FPGA_VERSION = 32'h03930124; // more hardware debug circuitry
// parameter FPGA_VERSION = 32'h03930123; // Implementing VSYNC/GPIO3 input
// parameter FPGA_VERSION = 32'h03930122; // Added debug output
// parameter FPGA_VERSION = 32'h03930121; // VOSPI setting MOSI to low, according to DS
// parameter FPGA_VERSION = 32'h03930120; // VOSPI
// parameter FPGA_VERSION = 32'h03930108; // parallel - in master branch
// parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, fixed bug, all met
// parameter FPGA_VERSION = 32'h03930110; //A serial - 17.4 - restored delay after linear, fixed bug, timing met
// parameter FPGA_VERSION = 32'h03930110; // serial - 17.4 - restored delay after linear, fixed bug, timing failed
// parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, fixed bug, all met
// parameter FPGA_VERSION = 32'h03930106; // parallel - 17.4 - increased delay after linear read all met
// parameter FPGA_VERSION = 32'h03930105; // parallel - 17.4 - fixed wide raw frames all met
// parameter FPGA_VERSION = 32'h03930104; // parallel - 17.4 - added RAW mode (for tiff files) timing met
......
......@@ -35,6 +35,9 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
// All paremeters should be defined for all defines values - needed to export to C
parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy
......@@ -152,14 +155,14 @@
parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE",
`ifdef use200Mhz
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
`ifdef MCLK_VCO_MULT
parameter CLKFBOUT_MULT = `MCLK_VCO_MULT ,
`else
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
`endif
`ifdef MCLK_VCO_MULT
parameter CLKFBOUT_MULT = `MCLK_VCO_MULT ,
`else
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
`endif
`else
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
......@@ -302,8 +305,16 @@
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
`ifdef SIMULATION
`ifdef LWIR
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 100, // initial delay value for start pulse
`else
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
`endif
`else
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
`endif
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h7f0,
......@@ -533,8 +544,63 @@
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_SLEW = "SLOW",
//`ifndef HISPI
//sensor_fifo parameters
//`ifdef HISPI
//`elsif LWIR
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_RST_SEQ = 2, // initiate reset cycle (master drives all sensors), generate frame start when ready
parameter VOSPI_SPI_SEQ = 3, // initilate SPI re-sync (will automatically generate frame syncs when re-synced)
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_OUT_EN = 8,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 10,
parameter VOSPI_RESET_ERR = 11,
parameter VOSPI_SPI_CLK = 12,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_SEGM0_OK = 14,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_VSYNC = 16,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 18, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_TELEMETRY = 20,
parameter VOSPI_TELEMETRY_BITS = 2,
parameter VOSPI_GPIO = 22,
parameter VOSPI_GPIO_BITS = 6,
parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
`ifdef SIMULATION
parameter VOSPI_SOF_TO_HACT = 1000, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF =1000, // pixel clock is 480 MHz, need to slow down for memory
`else
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`endif
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`ifdef SIMULATION
parameter VOSPI_MRST_MS = 1, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
`else
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`endif
//`else
//sensor_fifo parameters (for parallel12)
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
......@@ -567,6 +633,13 @@
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
`ifdef use200Mhz
parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
`else
......@@ -719,6 +792,8 @@
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
parameter CMPRS_CBIT_ROWS_LSB = 28, // bit # Four height LSBs in raw mode
parameter CMPRS_CBIT_ROWS_LSB_BITS = 4, // number of bits to control four height LSBs in raw mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
......@@ -737,7 +812,7 @@
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
......@@ -926,7 +1001,8 @@
parameter MULTICLK_DIV_XCLK = 12, // 100 MHz for compressor
parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz)
`else
parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
parameter MULTICLK_DIV_XCLK2X = 6, // unused value
`endif
parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping
// Additional parameters for multi-clock PLL (phases and buffer types)
......@@ -956,11 +1032,26 @@
parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz
`else
// Python program bug - does not support elseif??
`ifdef LWIR
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
`ifdef SIMULATION
parameter CLKOUT_DIV_PCLK = 2, //480 MHz // 4, // 240 MHz
parameter CLKOUT_DIV_PCLK2X = 1, //9060 MHz // 2, // 480 MHz
`else
parameter CLKOUT_DIV_PCLK = 96, // 10MHz // 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 48, // 20 MHz // 24, // 40 MHz
`endif
`else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
`endif
`endif
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
......
......@@ -54,6 +54,38 @@
`endif
parameter FCLK1_PERIOD = 0.0,
`ifdef LWIR
parameter LWIR_DATA_FILE1 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE2 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE3 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE4 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_WINDOW_WIDTH =160,
parameter LWIR_WINDOW_HEIGHT =120,
parameter LWIR_TELEMETRY = 2,
parameter LWIR_FRAME_PERIOD =946969,
parameter LWIR_FRAME_DELAY =100,
parameter LWIR_MS_PERIOD = 25, // 1us instead of 1 ms
parameter LWIR_TELEMETRY_REV = 16'h7654, // input[15:0]
parameter LWIR_TELEMETRY_STATUS = 32'h137f1248, // input[31:0]
parameter LWIR_TELEMETRY_SREV = 64'h0123456789abcdef, // input[63:0]
parameter LWIR_TELEMETRY_TEMP_COUTS = 16'd59000, // input[15:0]
parameter LWIR_TELEMETRY_TEMP_KELVIN = 16'd29500, // input[15:0]
parameter LWIR_TELEMETRY_TEMP_LAST_KELVIN = 16'd29300, // input[15:0]
parameter LWIR_TELEMETRY_TIME_LAST_MS = 32'h12345678, // input[31:0]
parameter LWIR_TELEMETRY_AGC_ROI_TOP = 16'd0, // input[15:0]
parameter LWIR_TELEMETRY_AGC_ROI_LEFT = 16'd0, // input[15:0]
parameter LWIR_TELEMETRY_AGC_ROI_BOTTOM = 16'd119, // input[15:0]
parameter LWIR_TELEMETRY_AGC_ROI_RIGHT = 16'd159, // input[15:0]
parameter LWIR_TELEMETRY_AGC_HIGH = 16'd19200, // input[15:0]
parameter LWIR_TELEMETRY_AGC_LOW = 16'd200, // input[15:0]
parameter LWIR_TELEMETRY_VIDEO_FORMAT = 32'haaaa5555, // input[31:0]
parameter LWIR_GPIO_IN = 4'b0000,
`endif
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
// parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288;
// parameter SENSOR12BITS_NROWS = 18, // 16; // 1032;
......
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_vospi.bit
-c specify_phys_memory
-i
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_vospi.bit
-c setupSensorsPower "VOSPI" all 0 0.1
-c measure_all "*DI"
-c setSensorClock 24.0 "2V5_LVDS"
-c set_rtc
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......@@ -183,9 +183,11 @@ class X393Camsync(object):
self.set_camsync_period (SYNC_BIT_LENGTH) #set (bit_length -1) (should be 2..255), not the period
if not isinstance(camsync_delay,list) or isinstance(camsync_delay,tuple):
camsync_delay = (camsync_delay, camsync_delay, camsync_delay, camsync_delay)
print ("camsync_delay=",camsync_delay)
for i, dly in enumerate (camsync_delay):
if not dly is None:
self.set_camsync_delay(sub_chn = i, delay = dly)
print ("set_camsync_delay(",i, dly,")")
if not camsync_period is None:
self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set
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......@@ -322,7 +322,9 @@ class X393ExportC(object):
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status",
data = [self._enc_status_sens_io(),self._enc_status_sens_io_hispi()],
data = [self._enc_status_sens_io(),
self._enc_status_sens_io_hispi(),
self._enc_status_sens_io_vospi()],
name = "x393_status_sens_io", typ="ro",
frmt_spcs = frmt_spcs)
......@@ -431,7 +433,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor port I/O control",
data = [self._enc_sensio_ctrl_par12(),
self._enc_sensio_ctrl_hispi()],
self._enc_sensio_ctrl_hispi(),
self._enc_sensio_ctrl_vospi()],
name = "x393_sensio_ctl", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
......@@ -1853,7 +1856,7 @@ class X393ExportC(object):
dw.append(("hact_ext_alive", 14, 1,0, "HACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
......@@ -1876,11 +1879,25 @@ class X393ExportC(object):
# dw.append(("rel_sol", 18, 3,0, "When SOL active on the last lane @ipclk, latches all other lanes SOL"))
# dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
# dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_io_vospi(self):
dw=[]
dw.append(("segment_id", 0, 4,0, "ID of the last received segment: 1-4 for the good frame, 0 - for ITAR-skipped frames"))
dw.append(("gpio_in", 4, 4,0, "Input from GPIO0-GPIO3, only GPIO3 may be used as segment ready"))
dw.append(("in_busy", 8, 1,0, "Frame segments are waited for or received to FIFO"))
dw.append(("out_busy", 9, 1,0, "received frame is being transferred to video memory"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by the command bit"))
dw.append(("sync_err", 11, 1,0, "At least 1 synchronization error happened since reset by the command bit"))
dw.append(("fake_in", 12, 1,0, "Just to keep hardware"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("busy", 25, 1,0, "in_busy OR out_busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......@@ -2107,6 +2124,38 @@ class X393ExportC(object):
dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value"))
return dw
def _enc_sensio_ctrl_vospi(self):
dw=[]
dw.append(("reset", vrlg.VOSPI_MRST, 2, 0, "Sensor reset/power down control (0 - NOP, 1 - power down + reset, 2 - no pwdn, reset, 3 - no pwdn, no reset"))
dw.append(("rst_seq", vrlg.VOSPI_RST_SEQ, 1, 0, "Initiate simultaneous all sensors reset, generate SOF after pause"))
dw.append(("spi_seq", vrlg.VOSPI_SPI_SEQ, 1, 0, "Initiate VOSPI reset, will generate normal SOF if successful"))
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))
dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory"))
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_err", vrlg.VOSPI_RESET_ERR, 1, 0, "Reset CRC and synchronization error status bits"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)"))
dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero"))
dw.append(("vsync_use", vrlg.VOSPI_VSYNC, 1, 0, "Wait for the VSYNC (GPIO3). Should be enabled via i2c"))
dw.append(("vsync_use_set",vrlg.VOSPI_VSYNC+1, 1, 0, "Enable vsync_use set/reset"))
dw.append(("noresync", vrlg.VOSPI_NORESYNC, 1, 0, "Disable re-synchronization by discard packets"))
dw.append(("noresync_set", vrlg.VOSPI_NORESYNC+1, 1, 0, "Enable noresync set/reset"))
dw.append(("telemetry", vrlg.VOSPI_TELEMETRY, 1, 0, "Receive telemetry (will hang if not enabled in Lepton)"))
dw.append(("telemetry_set",vrlg.VOSPI_TELEMETRY+1, 1, 0, "Enable telemetry set/reset"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
# dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("dbg_src", vrlg.VOSPI_DBG_SRC, 3, 0, " Hardware debug source:0-running,1-will_sync,2-vsync_rdy[1],3-discard_segment,4-in_busy,5-out_busy,6-hact,7-sof"))
dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src"))
return dw
def _enc_sensio_jtag(self):
dw=[]
dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level"))
......@@ -2319,6 +2368,8 @@ class X393ExportC(object):
dw.append(("bayer_set", vrlg.CMPRS_CBIT_BAYER, 1, 0, "Set 'bayer'"))
dw.append(("focus", vrlg.CMPRS_CBIT_FOCUS - vrlg.CMPRS_CBIT_FOCUS_BITS, vrlg.CMPRS_CBIT_FOCUS_BITS, 0, "Focus mode"))
dw.append(("focus_set", vrlg.CMPRS_CBIT_FOCUS, 1, 0, "Set 'focus'"))
dw.append(("rows_lsb", vrlg.CMPRS_CBIT_ROWS_LSB - vrlg.CMPRS_CBIT_ROWS_LSB_BITS, vrlg.CMPRS_CBIT_ROWS_LSB_BITS, 0, "4 LSBs of the (height-1), used in raw mode"))
dw.append(("rows_lsb_set", vrlg.CMPRS_CBIT_ROWS_LSB, 1, 0, "Set 4 LSBs of the (height-1)"))
return dw
def _enc_cmprs_coring_sel(self):
dw=[]
......@@ -2331,7 +2382,7 @@ class X393ExportC(object):
return dw
def _enc_cmprs_format(self):
dw=[]
dw.append(("num_macro_cols_m1", vrlg.CMPRS_FRMT_MBCM1, vrlg.CMPRS_FRMT_MBCM1_BITS, 0, "Number of macroblock colums minus 1"))
dw.append(("num_macro_cols_m1", vrlg.CMPRS_FRMT_MBCM1, vrlg.CMPRS_FRMT_MBCM1_BITS, 0, "Number of macroblock columns minus 1"))
dw.append(("num_macro_rows_m1", vrlg.CMPRS_FRMT_MBRM1, vrlg.CMPRS_FRMT_MBRM1_BITS, 0, "Number of macroblock rows minus 1"))
dw.append(("left_margin", vrlg.CMPRS_FRMT_LMARG, vrlg.CMPRS_FRMT_LMARG_BITS, 0, "Left margin of the first pixel (0..31) for 32-pixel wide colums in memory access"))
return dw
......
......@@ -46,6 +46,7 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
single = False,
reset_frame = False,
byte32 = True,
linear = False,
keep_open = False,
extra_pages = 0,
write_mem = False,
......@@ -61,6 +62,7 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
@param single - run single frame
@param reset_frame - reset frame number
@param byte32 - 32-byte columns (False - 16-byte columns) (not used in scanline mode)
@param linear - linear mode instead of tiled (for raw images)
@param keep_open- for 8 or less rows - do not close page between accesses (not used in scanline mode)
@param extra_pages 2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
This argument can be used for read access with horizontal overlapping tiles
......@@ -77,8 +79,8 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
rslt |= (extra_pages & ((1 << vrlg.MCONTR_LINTILE_EXTRAPG_BITS) - 1)) << vrlg.MCONTR_LINTILE_EXTRAPG
rslt |= (0,1)[keep_open] << vrlg.MCONTR_LINTILE_KEEP_OPEN
rslt |= (0,1)[byte32] << vrlg.MCONTR_LINTILE_BYTE32
rslt |= (0,1)[linear] << vrlg.MCONTR_LINTILE_LINEAR
rslt |= (0,1)[reset_frame] << vrlg.MCONTR_LINTILE_RST_FRAME
rslt |= (0,1)[single] << vrlg.MCONTR_LINTILE_SINGLE
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
......
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......@@ -200,7 +200,6 @@ module sens_parallel12 #(
// wire [18:0] status;
// wire [22:0] status;
wire [25:0] status; // added byte-wide xfpgatdo
wire cmd_we;
wire [2:0] cmd_a;
wire [31:0] cmd_data;
......
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/*!
* <b>Module:</b> vospi_packet_80
* @file vospi_packet_80.v
* @date 2019-04-08
* @author Andrey Filippov
*
* @brief VoSPI receive 160 byte packets
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* vospi_packet_80.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* vospi_packet_80.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module vospi_packet_80#(
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1 // do not output invalid packets data
)(
input rst,
input clk,
input start, // @posedge clk
output spi_clken, // enable clock on spi_clk
output spi_cs, // active low
input miso, // input from the sensor
input will_sync, // discard packet detected, sync_end will follow (from resync module)
output [15:0] dout, // 16-bit data received,valid at dv and 15 cycles after
output dv, // data valid strobe
output packet_done, // packet received,
output packet_busy, // packet busy (same as spi_clken, !spi_cs)
output crc_err, // crc error, valid with packet_done
output sync_err, // synchronization error, valid with packet_done
output [15:0] id, // packet ID (0x*f** - invlaid, if packet index = 20, 4 MSb - segment (- 0 invalid)
output packet_invalid, // set early, valid with packet done
output reg id_stb // id, packet invalid are set
);
reg [ 6:0] wcntr;
reg [ 3:0] bcntr;
wire pre_lsb_w;
reg lsb_r; // reading last bit from miso
reg copy_word; // copy 16-bit word from the SR (next after lsb_r);
reg [15:0] d_r;
reg [1:0] cs_r;
wire pre_last_w;
reg last_r;
reg [ 2:0] packet_end;
reg set_id_r;
reg set_crc_r;
reg set_d_r;
reg den_r;
reg [1:0] packet_header = 2'b11;
reg [15:0] d_sr;
reg [ 1:0] start_r;
reg dv_r;
reg [15:0] crc_r; // required crc
wire [15:0] crc_w; // current crc
reg [15:0] id_r;
wire [15:0] dmask;
reg packet_invalid_r;
reg will_sync_d;
wire sync_end; // last bit in a packet (turn off CS/spi_clken) (from resync module)
reg sync_err_r;
assign sync_end = !will_sync && will_sync_d; // trailing edge, so will fire if disabled
assign packet_busy = cs_r[0]; // clk_en_r;
assign spi_clken = cs_r[0]; // clk_en_r;
assign spi_cs = ~cs_r[0];
assign pre_lsb_w = bcntr == 4'he;
assign pre_last_w = pre_lsb_w && (wcntr == (VOSPI_PACKET_WORDS + 1));
assign packet_done = packet_end[2];
assign id = id_r;
// assign dmask = den_r ? 16'hffff: (wcntr[0]?16'h0: 16'h0fff);
assign dmask = packet_header[1] ? (packet_header[0] ? 16'h0fff: 16'h0) : 16'hffff ;
assign crc_err = packet_end[2] && (crc_r != crc_w) && !packet_invalid_r; // discard packets have 16'hffff in CRC field, do not record error
assign sync_err = packet_end[2] && sync_err_r;
assign dv = dv_r;
assign dout = d_r;
assign packet_invalid = packet_invalid_r;
always @ (posedge clk) begin
will_sync_d <= will_sync;
/// if (rst || packet_end[0]) cs_r[0] <= 0;
if (rst || packet_end[0] || sync_end) cs_r[0] <= 0;
else if (start) cs_r[0] <= 1;
cs_r[1] <= cs_r[0];
if (rst || !cs_r[0] || packet_end[0]) bcntr <= 0;
else bcntr <= bcntr + 1; // keep running even for sync
if (rst || !cs_r[0] || packet_end[0]) lsb_r <= 0;
else lsb_r <= pre_lsb_w; // generate even for sync
copy_word <= !rst && lsb_r;
if (rst || !cs_r[0] || packet_end[0]) wcntr <= 0;
else if (lsb_r) wcntr <= wcntr + 1; // keep running even for sync
if (rst || !cs_r[0] ) packet_end[1:0] <= 0;
/// else packet_end[1:0] <= {packet_end[0], pre_last_w};
else packet_end[1:0] <= {packet_end[0] | sync_end, pre_last_w & ~will_sync}; // do not generate premature if running sync
if (rst) packet_end[2] <= 0;
else packet_end[2] <= packet_end[1];
if (rst) start_r <= 0;
else start_r <= {start_r[0],start};
set_id_r <= !rst && (wcntr == 0) && lsb_r;
set_crc_r <= !rst && (wcntr == 1) && lsb_r;
set_d_r <= !rst && den_r && lsb_r;
if (rst || !cs_r[1] || packet_done) den_r <= 0;
else if (set_crc_r) den_r <= 1;
// if (cs_r[0]) d_sr <= {miso, d_sr[15:1]};
if (cs_r[0]) d_sr <= {d_sr[14:0],miso};
if (set_id_r) id_r <= d_sr;
if (set_crc_r) crc_r <= d_sr;
if (set_d_r) d_r <= d_sr;
dv_r <= set_d_r && !(packet_invalid_r && VOSPI_NO_INVALID);
if (rst || start) packet_invalid_r <= 0;
else if (will_sync) packet_invalid_r <= 1; // Will_sync disqualifies even started (erroneously) a good packet
else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf);
last_r <= pre_last_w;
if (rst || start) sync_err_r <= 0;
else if (sync_end && ! last_r) sync_err_r <= 1;
id_stb <= set_id_r;
if (rst || start || packet_done) packet_header <= 2'b11;
else if (copy_word) packet_header <= {packet_header[0], 1'b0};
end
crc16_x16x12x5x0 crc16_x16x12x5x0_i (
.clk (clk), // input
.srst (!cs_r[1]), // input
.en (copy_word), // input
.din (d_sr & dmask), // input[15:0]
.dout (crc_w) // output[15:0]
);
endmodule
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......@@ -68,7 +68,8 @@ module simul_lwir160x120_telemetry(
telemetry_rev [15:0], // word 0
telemetry_time [31:0], // words 1.. 2
telemetry_status [31:0], // words 3.. 4
{8{16'b0}}, // words 5..12
// {8{16'b0}}, // words 5..12
{16'h6110, 16'h8208, 16'h29a6, 16'h96a2, 16'h1045, 16'h076c, 16'h2400, 16'h0000 }, // words 5..12
telemetry_srev [63:0], // words 13..16
{3{16'b0}}, // words 17..19
telemetry_frame [31:0], // words 20..21
......
......@@ -64,6 +64,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define LWIR /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393
......
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......@@ -130,8 +130,8 @@ module timing393 #(
input lrst, // @ posedge lclk - sync reset
input ts_logger_snap, // request from the logger to take a snapshot
output ts_logger_stb, // one clock pulse before sending TS data
output [7:0] ts_logger_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
output [7:0] ts_logger_data, // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
output khz // 1 KHz 50% output
);
wire [3:0] frame_sync;
......@@ -180,7 +180,9 @@ module timing393 #(
.status_rq (status_rq), // output
.status_start (status_start), // input
.live_sec (live_sec), // output[31:0]
.live_usec (live_usec) // output[19:0]
.live_usec (live_usec), // output[19:0]
.khz (khz) // output
);
......
......@@ -161,7 +161,7 @@ module gpio393 #(
generate
genvar i;
for (i=0; i < GPIO_N; i=i+1) begin: gpio_block
gpio_bit gpio_bit_i (
gpio393_bit gpio_bit_i (
// .rst (rst), // input
.clk (mclk), // input
.srst (mrst), // input
......@@ -221,27 +221,3 @@ module gpio393 #(
endmodule
module gpio_bit (
// input rst, // global reset
input clk, // system clock
input srst, // @posedge clk - sync reset
input we,
input [1:0] d_in, // input bits
output d_out, // output data
output en_out); // enable output
reg d_r = 0;
reg en_r = 0;
assign d_out = d_r;
assign en_out = en_r;
always @ (posedge clk) begin
if (srst) d_r <= 0;
else if (we && (|d_in)) d_r <= !d_in[0];
if (srst) en_r <= 0;
else if (we && (|d_in)) en_r <= !(&d_in);
end
endmodule
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