...
 
Commits (67)
......@@ -66,4 +66,5 @@ html.tar.gz
/sysroots
/image
/scripts
py393-p2
*.~*
......@@ -24,6 +24,10 @@ COMMAND_FILES = py393/hargs \
py393/hargs-after \
py393/hargs-eyesis \
py393/hargs-hispi \
py393/hargs-vospi \
py393/hargs-post-vospi \
py393/hargs-boson \
py393/hargs-post-boson \
py393/hargs-post-par12 \
py393/hargs-power_par12 \
py393/hargs-power-eyesis \
......
from cocotb import x393_cocotb3_server
from __future__ import print_function
from __future__ import division
"""
# Copyright (C) 2016, Elphel.inc.
# Simulation code for cocotb simulation for x393 project
......@@ -86,15 +87,18 @@ class x393Client():
self.PORT = port
self.HOST = host # Symbolic name meaning all available interfaces
self.cmd= SocketCommand()
# print("HOST=%s"%(self.HOST))
# print("PORT=%d"%(self.PORT))
def communicate(self, snd_str):
sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
sock.connect((self.HOST, self.PORT))
sock.send(snd_str)
reply = sock.recv(16384) # limit reply to 16K
sock.send(snd_str.encode('iso-8859-1'))
reply = sock.recv(16384).decode('iso-8859-1') # limit reply to 16K
sock.close()
return reply
def start(self):
self.cmd.setStart()
# print(self.cmd.toJSON()) #{"cmd": "start", "args": null}
print("start->",self.communicate(self.cmd.toJSON()))
def stop(self):
self.cmd.setStop()
......
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from __future__ import print_function
from __future__ import division
"""
# Copyright (C) 2016, Elphel.inc.
# Simulation code for cocotb simulation for x393 project
......
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from __future__ import print_function
from __future__ import division
"""
......@@ -179,9 +180,9 @@ class SAXIWrSim(BusDriver):
# self.log.debug ("SAXIWrSim.__init__(): super done")
#Open file to use as system memory
try:
self._memfile=open(mempath, 'r+') #keep old file if it exists already
self._memfile=open(mempath, 'rb+') #keep old file if it exists already
except:
self._memfile=open(mempath, 'w+') #create a new file if it does not exist
self._memfile=open(mempath, 'wb+') #create a new file if it does not exist
self.log.info ("SAXIWrSim(%s): created a new 'memory' file %s"%(name,mempath)) #
#Extend to full size
self._memfile.seek(memhigh-1)
......@@ -254,7 +255,8 @@ class SAXIWrSim(BusDriver):
bv = self.bus.wr_data.value
bv.binstr = re.sub("[^1]","0",bv.binstr)
data = bv.integer
sdata=struct.pack(self._fmt,data)
# sdata=struct.pack(self._fmt,data).decode('iso-8859-1')
sdata = data.to_bytes(self._data_bytes, byteorder='little') # byte array
bv = self.bus.wr_data.value
bv.binstr= re.sub("[^0]","1",bv.binstr) # only 0 suppresses write to this byte
while len(bv.binstr) < self._data_bytes: # very unlikely
......@@ -264,9 +266,9 @@ class SAXIWrSim(BusDriver):
else:
for i in range (self._data_bytes):
if bv.binstr[-1-i] != 0:
self._memfile.write(sdata[i])
self._memfile.write(sdata[i:i+1])
else:
self._memfile.seek(1,1)
self._memfile.seek(1,1)
if self.autoflush:
self._memfile.flush()
self.log.info ("SAXIWrSim(%s:%d) 0x%x <- 0x%x"%(self.name,self._data_bytes,address,data))
......@@ -382,7 +384,8 @@ class SAXIRdSim(BusDriver):
rs = None
if not rs is None:
try:
data = struct.unpack(self._fmt,rs)
# data = struct.unpack(self._fmt,rs)
data = int.from_bytes(rs, byteorder='little')
except:
self.log.warning ("SAXIRdSim():Can not unpack memory data @ address 0x%08x"%(address))
data=None
......
......@@ -129,6 +129,8 @@ module cmprs_cmd_decode#(
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
parameter CMPRS_CBIT_ROWS_LSB = 28, // bit # Four height LSBs in raw mode
parameter CMPRS_CBIT_ROWS_LSB_BITS = 4, // number of bits to control four height LSBs in raw mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
......@@ -205,6 +207,7 @@ module cmprs_cmd_decode#(
output reg [ 2:0] cmprs_qpage, // [2:0] - quantizator page number (0..7)
output reg cmprs_dcsub, // subtract dc level before DCT, restore later
output reg [ 1:0] cmprs_fmode, //[1:0] - focus mode
output reg [ 3:0] raw_rows_lsb, // Four LSBs of the window height - used in raw mode
output reg [ 1:0] bayer_shift, // additional shift to bayer mosaic
output reg ignore_color,
......@@ -246,6 +249,7 @@ module cmprs_cmd_decode#(
reg cmprs_dcsub_mclk; // subtract dc level before DCT, restore later
reg [ 3:0] cmprs_mode_mclk; // [3:0] - compressor mode
reg [ 1:0] cmprs_fmode_mclk; //[1:0] - focus mode
reg [ 3:0] rows_lsb_mclk; // [3:0] - Four LSBs of the window height - used in raw mode
reg [ 1:0] bayer_shift_mclk; // additional shift to bayer mosaic
reg [30:0] format_mclk; // left margin and macroblock rows/columns
......@@ -256,6 +260,8 @@ module cmprs_cmd_decode#(
reg cmprs_dcsub_xclk; // subtract dc level before DCT, restore later
reg [ 3:0] cmprs_mode_xclk; // [3:0] - compressor mode
reg [ 1:0] cmprs_fmode_xclk; //[1:0] - focus mode
reg [ 3:0] rows_lsb_xclk; // Four LSBs of the window height - used in raw mode
reg [ 1:0] bayer_shift_xclk; // additional shift to bayer mosaic
reg [30:0] format_xclk; // left margin and macroblock rows/columns
......@@ -311,6 +317,9 @@ module cmprs_cmd_decode#(
if (mrst) cmprs_fmode_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FOCUS]) cmprs_fmode_mclk <= di_r[CMPRS_CBIT_FOCUS-1 -:CMPRS_CBIT_FOCUS_BITS];
if (mrst) rows_lsb_mclk <= 4'hf;
else if (ctrl_we_r && di_r[CMPRS_CBIT_ROWS_LSB]) rows_lsb_mclk <= di_r[CMPRS_CBIT_ROWS_LSB-1 -:CMPRS_CBIT_ROWS_LSB_BITS];
if (mrst) bayer_shift_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_BAYER]) bayer_shift_mclk <= di_r[CMPRS_CBIT_BAYER-1 -:CMPRS_CBIT_BAYER_BITS];
......@@ -343,6 +352,7 @@ module cmprs_cmd_decode#(
cmprs_dcsub_xclk <= cmprs_dcsub_mclk;
cmprs_mode_xclk <= cmprs_mode_mclk;
cmprs_fmode_xclk <= cmprs_fmode_mclk;
rows_lsb_xclk <= rows_lsb_mclk;
bayer_shift_xclk <= bayer_shift_mclk;
end
......@@ -356,6 +366,7 @@ module cmprs_cmd_decode#(
cmprs_qpage <= cmprs_qpage_xclk;
cmprs_dcsub <= cmprs_dcsub_xclk;
cmprs_fmode <= cmprs_fmode_xclk;
raw_rows_lsb <= rows_lsb_xclk;
bayer_shift <= bayer_shift_xclk;
left_marg <= format_xclk[CMPRS_FRMT_LMARG +: CMPRS_FRMT_LMARG_BITS];
......
......@@ -62,7 +62,8 @@ module cmprs_raw_buf_iface #(
input cmprs_run_mclk, // 0 - off or stopping, reset frame_pre_run
// input [ 4:0] left_marg, // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile)
input [12:0] n_blocks_in_row_m1, // number of macroblocks in a macroblock row minus 1
input [12:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1
// input [12:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1
input [16:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1
input stuffer_running, // @xclk, active while bit stuffer or trailer are running
input raw_be16, // 0: bytes 0-1-2-3-4-5..., 1: bytes 1-0-3-2-5-4...
output [11:0] buf_ra, // buffer read address (2 MSB - page number)
......@@ -206,7 +207,8 @@ module cmprs_raw_buf_iface #(
quad_last <= mode_valid && !(|quads_left); // valid from 2 after frame_pre_start_r or after quad_r[3]
if (frame_pre_start_r) rows_left <= {n_block_rows_m1, 4'b1111};
// if (frame_pre_start_r) rows_left <= {n_block_rows_m1, 4'b1111};
if (frame_pre_start_r) rows_left <= n_block_rows_m1; //n_block_rows_m1 now combines n_block_rows_m1 and tile vstep ?
else if ((quad_r[2] && quad_last)) rows_left <= rows_left - 1;
rows_last <= {rows_last[0], mode_valid & ~(|rows_left)};
......
......@@ -84,6 +84,9 @@ module compressor393 # (
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
parameter CMPRS_CBIT_ROWS_LSB = 28, // bit # Four height LSBs in raw mode
parameter CMPRS_CBIT_ROWS_LSB_BITS = 4, // number of bits to control four height LSBs in raw mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
......@@ -382,6 +385,8 @@ module compressor393 # (
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
.CMPRS_CBIT_FOCUS_BITS (CMPRS_CBIT_FOCUS_BITS),
.CMPRS_CBIT_ROWS_LSB (CMPRS_CBIT_ROWS_LSB),
.CMPRS_CBIT_ROWS_LSB_BITS (CMPRS_CBIT_ROWS_LSB_BITS),
.CMPRS_CBIT_RUN_RST (CMPRS_CBIT_RUN_RST),
.CMPRS_CBIT_RUN_STANDALONE (CMPRS_CBIT_RUN_STANDALONE),
.CMPRS_CBIT_RUN_ENABLE (CMPRS_CBIT_RUN_ENABLE),
......
......@@ -78,6 +78,8 @@ module jp_channel#(
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
parameter CMPRS_CBIT_ROWS_LSB = 28, // bit # Four height LSBs in raw mode
parameter CMPRS_CBIT_ROWS_LSB_BITS = 4, // number of bits to control four height LSBs in raw mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
......@@ -245,7 +247,7 @@ module jp_channel#(
wire jp4_dc_improved; // in JP4 mode, compare DC coefficients to the same color ones
// wire [ 1:0] tile_margin; // margins around 16x16 tiles (0/1/2)
// wire [ 2:0] tile_shift; // tile shift from top left corner
wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 7 - mono8 (not yet implemented)
wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 6 - raw, 7 - mono8 (not yet implemented)
wire scale_diff; // divide differences by 2 (to fit in 8-bit range)
wire hdr; // second green absolute, not difference
wire subtract_dc; // subtract/restore DC components
......@@ -253,7 +255,7 @@ module jp_channel#(
wire [CMPRS_CSAT_CR_BITS-1:0] m_cr; // [9:0] scale for CR - default 0.713 (10'hb6)
wire [ 1:0] cmprs_fmode; // focusing/overlay mode
wire [ 3:0] raw_rows_lsb; // four LSBs of window height in raw mode, 0 means 'h10, 'hf means f
//TODO: assign next 5 values from converter_type[2:0]
wire [ 5:0] mb_w_m1; // macroblock width minus 1
wire [ 5:0] mb_h_m1; // macroblock height -1
......@@ -701,6 +703,8 @@ module jp_channel#(
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
.CMPRS_CBIT_FOCUS_BITS (CMPRS_CBIT_FOCUS_BITS),
.CMPRS_CBIT_ROWS_LSB (CMPRS_CBIT_ROWS_LSB),
.CMPRS_CBIT_ROWS_LSB_BITS (CMPRS_CBIT_ROWS_LSB_BITS),
.CMPRS_CBIT_RUN_RST (CMPRS_CBIT_RUN_RST),
.CMPRS_CBIT_RUN_STANDALONE (CMPRS_CBIT_RUN_STANDALONE),
.CMPRS_CBIT_RUN_ENABLE (CMPRS_CBIT_RUN_ENABLE),
......@@ -760,7 +764,8 @@ module jp_channel#(
.cmprs_en_late_xclk (stuffer_en), // output reg - extended enable to allow stuffer to gracefully finish
.cmprs_qpage (cmprs_qpage), // output[2:0] reg
.cmprs_dcsub (subtract_dc), // output reg
.cmprs_fmode (cmprs_fmode), // output[1:0] reg
.cmprs_fmode (cmprs_fmode), // output[1:0] reg
.raw_rows_lsb (raw_rows_lsb), // output[3:0] reg
.bayer_shift (bayer_phase), // output[1:0] reg
.ignore_color (ignore_color), // output reg
.four_blocks (), // output reg Not used?
......@@ -888,7 +893,7 @@ module jp_channel#(
.frame_go (frame_go_raw), // input
.cmprs_run_mclk (cmprs_run_mclk), // input
.n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0]
.n_block_rows_m1 (n_block_rows_m1), // input[12:0]
.n_block_rows_m1 ({n_block_rows_m1,raw_rows_lsb}), // input[12:0]
.stuffer_running (stuffer_running), // input
.raw_be16 (raw_be16), // input
.buf_ra (raw_buf_ra), // output[11:0]
......
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......@@ -53,6 +53,48 @@
parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif
parameter FCLK1_PERIOD = 0.0,
// for python (export to C header) all parameters should be defined
//`ifdef LWIR
parameter LWIR_DATA_FILE1 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE2 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE3 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE4 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_WINDOW_WIDTH =160,
parameter LWIR_WINDOW_HEIGHT =120,
parameter LWIR_TELEMETRY = 2,
parameter LWIR_FRAME_PERIOD =946969,
parameter LWIR_FRAME_DELAY =100,
parameter LWIR_MS_PERIOD = 25, // 1us instead of 1 ms
parameter LWIR_TELEMETRY_REV = 16'h7654, // input[15:0]
parameter LWIR_TELEMETRY_STATUS = 32'h137f1248, // input[31:0]
parameter LWIR_TELEMETRY_SREV = 64'h0123456789abcdef, // input[63:0]
parameter LWIR_TELEMETRY_TEMP_COUTS = 16'd59000, // input[15:0]
parameter LWIR_TELEMETRY_TEMP_KELVIN = 16'd29500, // input[15:0]
parameter LWIR_TELEMETRY_TEMP_LAST_KELVIN = 16'd29300, // input[15:0]
parameter LWIR_TELEMETRY_TIME_LAST_MS = 32'h12345678, // input[31:0]
parameter LWIR_TELEMETRY_AGC_ROI_TOP = 16'd0, // input[15:0]
parameter LWIR_TELEMETRY_AGC_ROI_LEFT = 16'd0, // input[15:0]
parameter LWIR_TELEMETRY_AGC_ROI_BOTTOM = 16'd119, // input[15:0]
parameter LWIR_TELEMETRY_AGC_ROI_RIGHT = 16'd159, // input[15:0]
parameter LWIR_TELEMETRY_AGC_HIGH = 16'd19200, // input[15:0]
parameter LWIR_TELEMETRY_AGC_LOW = 16'd200, // input[15:0]
parameter LWIR_TELEMETRY_VIDEO_FORMAT = 32'haaaa5555, // input[31:0]
parameter LWIR_GPIO_IN = 4'b0000,
parameter BOSON_DATA_FILE = "/input_data/pattern_160_120_16.dat",
parameter BOSON_WIDTH = 160, // 640
parameter BOSON_HEIGHT = 120, // 513
parameter BOSON_OUT_BITS = 16, // 16
parameter BOSON_FPS = 60.0, // 60.0
parameter BOSON_HSW = 8, // 8
parameter BOSON_FP_BP = 22, // 102 (FP+BP)
parameter BOSON_FP = 12, // 52
parameter BOSON_VSW = 7, // 87, // in scan lines
//`endif
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
// parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288;
......@@ -160,9 +202,16 @@
parameter HISTOGRAM_START_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
`ifdef LWIR
parameter WOI_WIDTH= 160,
parameter WOI_HEIGHT= 122,
`elsif BOSON
parameter WOI_WIDTH= 160, // 640,
parameter WOI_HEIGHT= 120, // 513,
`else
parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64,
parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32,
`endif
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 1000
//
// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.tiff
// autogenerated from ../input_data/pattern_160_120_14.tiff
// GENERATOR = ./x393_tiff_verilog.py
// WIDTH = 160
// HEIGHT = 120
//
160e 3189 3348 3256 3201 31ef 3258 324e 32e9 333d 3365 3427 3690 2714 13d1 0e40 11f6 3293 334b 31f1 31d0 31e8 3210 31bb 3173 31ec 3255 3264 3301 33d1 3568 16c0 0dd6 103b 1092 10fa 10e2 115e 1206 11f6 1123 10d7 0ff5 10e3 2c2c 3435 3288 33c3 3738 252f 0dcf 0dc3 0e3e 0eab 0f5b 104b 1008 0ebb 0cd8 0b4f 0f2c 2a2e 3436 3257 3241 31f4 321c 3376 340f 207a 093e 0c08 0ec9 0f59 0fac 0fb8 102f 0e98 27f6 3774 34b2 33be 3369 3325 3349 33f8 34eb 3591 35d4 35f8 362f 366f 3610 35c1 3555 34b1 3452 3429 33d1 33a5 32a8 326d 321a 322b 356e 1fed 09cc 0d1a 0d85 0d33 0dca 0e00 0e5e 0db4 0ed4 0ec7 0e85 0e54 0dfe 0e97 0e35 0e42 0e84 0f0b 1005 100b 10d7 1104 112c 125b 283b 37fd 34f5 3507 34f9 354c 34ee 3454 343d 3432 3483 34d9 34c3 3505 34fb 3458 3437 33f4 3443 3403 33ad 3308 1ffc 0d7a 073e 09b4 0c84 0c16 0b3e 0be4
31bf 338b 329a 32f6 3291 329b 32c0 3300 3379 33a2 341d 363c 21a5 0fbb 0f56 0fbf 0e6c 2a60 35fe 3208 31a3 31b9 31ff 316b 318f 323c 3218 31c5 3230 347b 2f16 0df8 0ef1 1035 1042 0ffc 1028 1038 10a3 115b 10c8 1022 0f16 0b78 1eeb 37bd 364d 3456 21fd 0d92 0d53 0eac 0f8c 0fc1 0fb5 0f6c 0ea7 0cd1 0b4f 0d9b 2c75 3440 31cc 324a 3242 3280 3288 3287 329b 35d3 223f 09b4 0ea6 1048 10fa 1141 0fee 1185 3265 36a2 34a1 3464 33d9 3394 33a2 345e 34ee 358f 35c7 364a 375e 38d5 3907 385b 365e 352f 3503 3483 3407 33bd 3344 32bd 32eb 3249 3533 24d2 0a3c 0c79 0dc0 0e67 0ee4 0f46 0f25 0f4c 0f85 0e7d 0e98 0d7a 0d89 0e5a 0edb 0f35 0fc2 0fa5 1081 1059 10b6 1124 10d6 1141 15b1 33d9 3766 35e0 3564 356c 34c7 34ac 3484 34a5 34a2 34de 350b 34cc 3505 345c 343c 3417 3411 3416 339f 33c0 353e 317b 2298 0cc7 0946 0be2 0c17 0c41
......
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......@@ -264,6 +264,7 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCONTR_LINTILE_NO_PENDING = 16, // ignore new frame start if previous frame is not finished
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024 // initial delay value for start pulse
......@@ -1122,6 +1123,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
) mcntrl_linear_wr_sensor_i (
......@@ -1281,6 +1283,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
......@@ -1357,6 +1360,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
) mcntrl_linear_rw_chn3_i (
......
......@@ -80,7 +80,8 @@ module mcntrl_linear_rw #(
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCONTR_LINTILE_NO_PENDING = 15, // ignore new frame start if previous frame is not finished
// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
......@@ -182,6 +183,7 @@ module mcntrl_linear_rw #(
wire chn_rst; // resets command, including fifo;
reg chn_rst_d; // delayed by 1 cycle do detect turning off
wire abort_en; // enable frame abort (mode register bit)
wire no_pending; // ignore new frame start if previous frame is not finished
reg aborting_r; // waiting pending memory transactions at if the frame was not finished at frame sync
// reg xfer_reset_page_r;
reg xfer_page_rst_r=1;
......@@ -245,7 +247,7 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
reg [14:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [16:0] mode_reg;//mode register: {no_pending,abort_en,copy_frame,skip_too_late,dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
......@@ -302,7 +304,7 @@ module mcntrl_linear_rw #(
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[14:0]; // 4:0]; // [4:0];
else if (set_mode_w) mode_reg <= cmd_data[16:0]; // 4:0]; // [4:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
......@@ -429,6 +431,7 @@ module mcntrl_linear_rw #(
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE];
assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE];
assign no_pending = mode_reg[MCONTR_LINTILE_NO_PENDING];
`ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
assign status_data= {last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
......@@ -490,10 +493,10 @@ module mcntrl_linear_rw #(
// if (mrst || frame_start_delayed) frame_start_pending <= 0;
if (mrst) frame_start_pending <= 0;
// else frame_start_pending <= {frame_start_pending[0], busy_r && (frame_start_pending[0] | frame_start_late)};
else frame_start_pending <= busy_r && (frame_start_pending | frame_start_late);
else frame_start_pending <= !no_pending && busy_r && (frame_start_pending | frame_start_late);
if (mrst) frame_start_pending_long <= 0;
else frame_start_pending_long <= {frame_start_pending_long[0], (busy_r || skip_run) && (frame_start_pending_long[0] | frame_start_late)};
else frame_start_pending_long <= {frame_start_pending_long[0], ~no_pending & (busy_r | skip_run) && (frame_start_pending_long[0] | frame_start_late)};
if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};
......
......@@ -192,7 +192,7 @@ dm_single #(
.din(din_dm_r[3:0]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly_dm) // clk_div synchronous set odealy value from loaded
.ld_odelay(ld_odly_dm) // clk_div synchronous set odealy value from loaded
);
`ifdef NOFINEDELAY_DQS
......
......@@ -61,8 +61,8 @@ module dqs_single_nofine #(
input [7:0] dly_data,
input [3:0] din,
input [3:0] tin,
input set_odelay,
input ld_odelay,
input set_odelay, // apply loaded pipeline register data
input ld_odelay, // load pipeline register data
input set_idelay,
input ld_idelay
);
......@@ -113,6 +113,7 @@ IOBUFDS_DCIEN #(
.IBUFDISABLE(1'b0),
.I(dqs_data_dly), //dqs_data),
.T(dqs_tri));
idelay_nofine # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(IDELAY_VALUE>>3),
......
......@@ -14,11 +14,4 @@
<natures>
<nature>org.python.pydev.pythonNature</nature>
</natures>
<linkedResources>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data_ssd/nc393/elphel393/fpga-elphel/x393/py393/vivado_logs/VivadoSynthesis-20190404120819591.log</location>
</link>
</linkedResources>
</projectDescription>
eclipse.preferences.version=1
encoding/import_verilog_parameters.py=utf-8
encoding/test_mcntrl.py=utf-8
encoding/x393_tiff_verilog.py=utf-8
-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh ../includes/x393_simulation_parameters.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-i
#!/usr/bin/env python3
# encoding: utf-8
'''
# Copyright (C) 2020, Elphel.inc.
# test for import_verilog_parameters.py
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2020 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
CRC16_XMODEM_TABLE =[
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0]
def create_with_parity (init_data, # numeric data (may be less than full array
num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
# start_bit, # bit number to start filling from
full_bram): # true if ramb36, false - ramb18
d = num_bits
num_bits8 = 1;
while d > 1:
d >>= 1
num_bits8 <<= 1
bsize = (0x4000,0x8000)[full_bram]
bdata = [0 for i in range(bsize)]
sb = 0
for item in init_data:
for bt in range (num_bits8):
bdata[sb+bt] = (item >> bt) & 1;
sb += num_bits8
data = []
for i in range (len(bdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + bdata[256*i+b]
data.append(d)
data_p = []
num_bits_p = num_bits8 >> 3
sb = 0
print ("num_bits=",num_bits)
print ("num_bits8=",num_bits8)
print ("num_bits_p=",num_bits_p)
if num_bits_p:
pbsize = bsize >> 3
pbdata = [0 for i in range(pbsize)]
for item in init_data:
# print ("item = 0x%x, p = 0x%x"%(item,item >> num_bits8))
for bt in range (num_bits_p):
pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;
# print ("pbdata[%d] = 0x%x"%(sb+bt, pbdata[sb+bt]))
sb += num_bits_p
for i in range (len(pbdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + pbdata[256*i+b]
data_p.append(d)
# print(bdata)
# print(data)
# print(pbdata)
# print(data_p)
return {'data':data,'data_p':data_p}
def print_params(data,out_file_name):
with open(out_file_name,"w") as out_file:
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
def print_params(data):
print("Paste following to memory parameters in Verilog source file:")
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v))
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v))
rslt = create_with_parity (CRC16_XMODEM_TABLE, # init_data, # numeric data (may be less than full array
16, # num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
False) #full_bram): # true if ramb36, false - ramb18
print_params(rslt)#,"test.vh")
# from FLIR docs:
def crc16(data, crc=0x1d0f): #Note the new initial condition is 0x1d0f instead of 0.
# in C:return(USHORT)((crcin << 8) ^ ccitt_16Table[((crcin >> 8)^(data))&255]);
for byte in data:
crc = ((crc << 8) & 0xff00) ^ CRC16_XMODEM_TABLE[((crc >> 8) & 0xff) ^ byte]
return crc & 0xffff
from __future__ import print_function
from __future__ import division
'''
Created on Mar 23, 2015
......
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_boson.bit
-c setupSensorsPower "BOSON" all 0 0.1
-c measure_all "*DI"
-c setSensorClock 24.0 "1V8_LVDS"
-c set_rtc
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_boson.bit
-c specify_phys_memory
-i
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_vospi.bit
-c specify_phys_memory
-i
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_vospi.bit
-c setupSensorsPower "VOSPI" all 0 0.1
-c measure_all "*DI"
-c setSensorClock 24.0 "2V5_LVDS"
-c set_rtc
#!/usr/bin/env python
#!/usr/bin/env python3
from __future__ import division
from __future__ import print_function
'''
......@@ -32,7 +32,8 @@ __email__ = "andrey@elphel.com"
__status__ = "Development"
import os
import urlparse
#import urlparse
import urllib
import time
import socket
import shutil
......@@ -50,7 +51,7 @@ def communicate(port,snd_str):
sock.close()
return reply
try:
qs=urlparse.parse_qs(os.environ['QUERY_STRING'])
qs=urllib.parse.parse_qs(os.environ['QUERY_STRING'])
except:
print("failed in os.environ['QUERY_STRING']")
qs={}
......
from __future__ import print_function
from __future__ import division
'''
# Copyright (C) 2015, Elphel.inc.
# Parsing Verilog parameters from the header files
......@@ -198,7 +200,8 @@ class ImportVerilogParameters(object):
c=getNextChar()
if c is None:
return None
c=string.lower(c)
# c=string.lower(c)
c=c.lower()
if not (c in "bodh"):
return None
if c=="b":
......@@ -265,7 +268,8 @@ class ImportVerilogParameters(object):
c=getNextChar()
if c is None:
break
c=string.lower(c)
# c=string.lower(c)
c=c.lower()
if not c in nChars:
cp[0]-=1
break
......@@ -317,7 +321,10 @@ class ImportVerilogParameters(object):
def binop_mult(exp1,exp2):
return (exp1[0] * exp2[0],exp1[1]+exp2[1])
def binop_div(exp1,exp2):
return (exp1[0] / exp2[0],exp1[1])
if isinstance(exp1[0], (int,)) and isinstance(exp2[0], (int,)):
return (exp1[0] // exp2[0], exp1[1])
else:
return (exp1[0] / exp2[0],exp1[1])
def binop_mod(exp1,exp2):
return (exp1[0] % exp2[0],exp2[1])
def binop_lshift(exp1,exp2):
......@@ -440,7 +447,7 @@ class ImportVerilogParameters(object):
print ("line=%s"%(line))
print ()
# print ("exp=%s"%(str(exp)))
if isinstance(exp[0],(int,long)):
if isinstance(exp[0],(int,)):
width=getParWidth(exp[1])
elif isinstance(exp[0],str):
width=8*len(exp[0])
......@@ -510,7 +517,7 @@ class ImportVerilogParameters(object):
self.conditions.append(not self.conditions.pop())
continue
elif tokens[0] == "elsif":
self.conditions.pop
self.conditions.pop()
self.conditions.append((tokens[1] in self.defines) and ( not False in self.conditions))
continue
else: # enabled, process all directives
......@@ -521,7 +528,7 @@ class ImportVerilogParameters(object):
self.conditions.append(not (tokens[1] in self.defines))
continue
elif tokens[0] == "elsif":
self.conditions.pop
self.conditions.pop()
self.conditions.append(tokens[1] in self.defines)
continue
elif tokens[0] == "else":
......@@ -741,4 +748,4 @@ class ImportVerilogParameters(object):
return self.parameters
def getDefines(self):
return self.defines
\ No newline at end of file
#!/usr/bin/env python
#!/usr/bin/env python3
from __future__ import division
from __future__ import print_function
'''
Generates window settings for driverless mode
......@@ -104,8 +106,8 @@ y_end = y_start + y_output_size - 1 + compressor_margin
frame_length_lines = y_output_size + min_frame_blanking_lines
llp0 = min_line_length_pck
llp1 = x_output_size/2+min_line_blanking_pck/2
llp2 = x_output_size/2+0x5e
llp1 = x_output_size//2+min_line_blanking_pck//2
llp2 = x_output_size//2+0x5e
line_length_pck = max(llp0,llp1,llp2)
......
, .INIT_00 (256'hF1EFE1CED1ADC18CB16BA14A9129810870E760C650A540843063204210210000)
, .INIT_01 (256'hE3DEF3FFC39CD3BDA35AB37B8318933962D672F7429452B52252327302101231)
, .INIT_02 (256'hD58DC5ACF5CFE5EE95098528B54BA56A548544A474C764E61401042034432462)
, .INIT_03 (256'hC7BCD79DE7FEF7DF87389719A77AB75B46B4569566F676D70630161126723653)
, .INIT_04 (256'hB92BA90A99698948F9AFE98ED9EDC9CC382328021861084078A7688658E548C4)
, .INIT_05 (256'hAB1ABB3B8B589B79EB9EFBBFCBDCDBFD2A123A330A501A716A967AB74AD45AF5)
, .INIT_06 (256'h9D498D68BD0BAD2ADDCDCDECFD8FEDAE1C410C603C032C225CC54CE47C876CA6)
, .INIT_07 (256'h8F789F59AF3ABF1BCFFCDFDDEFBEFF9F0E701E512E323E134EF45ED56EB67E97)
, .INIT_08 (256'h606770464025500420E330C200A11080E16FF14EC12DD10CA1EBB1CA81A99188)
, .INIT_09 (256'h725662775214423532D222F3129002B1F35EE37FD31CC33DB3DAA3FB939883B9)
, .INIT_0A (256'h4405542464477466048114A024C334E2C50DD52CE54FF56E858995A8A5CBB5EA)
, .INIT_0B (256'h563446157676665716B0069136F226D3D73CC71DF77EE75F97B88799B7FAA7DB)
, .INIT_0C (256'h28A3388208E118C06827780648655844A9ABB98A89E999C8E92FF90EC96DD94C)
, .INIT_0D (256'h3A922AB31AD00AF17A166A375A544A75BB9AABBB9BD88BF9FB1EEB3FDB5CCB7D)
, .INIT_0E (256'h0CC11CE02C833CA24C455C646C077C268DC99DE8AD8BBDAACD4DDD6CED0FFD2E)
, .INIT_0F (256'h1EF00ED13EB22E935E744E557E366E179FF88FD9BFBAAF9BDF7CCF5DFF3EEF1F)
#!/usr/bin/env python
#!/usr/bin/env python3
# encoding: utf-8
'''
# Copyright (C) 2015, Elphel.inc.
......@@ -23,7 +23,8 @@
@deffield updated: Updated
'''
from __future__ import print_function
from __builtin__ import str
from __future__ import division
#from __builtin__ import str
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
......@@ -37,7 +38,7 @@ __status__ = "Development"
'''
import readline
#import readline
import sys
import os
import inspect
......@@ -102,20 +103,10 @@ class CLIError(Exception):
def extractTasks(obj,inst):
for name in obj.__dict__:
if hasattr((obj.__dict__[name]), '__call__') and not (name[0]=='_'):
# print (name+" -->"+str(obj.__dict__[name]))
# print (obj.__dict__[name].func_code)
# print ("COMMENTS:"+str(inspect.getcomments(obj.__dict__[name])))
# print ("DOCS:"+str(inspect.getdoc(obj.__dict__[name])))
func_args=obj.__dict__[name].func_code.co_varnames[1:obj.__dict__[name].func_code.co_argcount]
# print("%s: %d, varnames=%s func_args=%s, defaults=%s"%
# (name,
# obj.__dict__[name].func_code.co_argcount,
# str(obj.__dict__[name].func_code.co_varnames),
# str(func_args),
# obj.__dict__[name].func_defaults))
func_args=obj.__dict__[name].__code__.co_varnames[1:obj.__dict__[name].__code__.co_argcount]
callableTasks[name]={'func':obj.__dict__[name],
'args':func_args,
'dflts':obj.__dict__[name].func_defaults,
'dflts':obj.__dict__[name].__defaults__,
'inst':inst,
'docs':inspect.getdoc(obj.__dict__[name])}
def execTask(commandLine):
......@@ -301,7 +292,7 @@ USAGE
except KeyboardInterrupt:
### handle keyboard interrupt ###
return 0
except Exception, e:
except Exception as e:
if DEBUG or TESTRUN:
raise(e)
indent = len(program_name) * " "
......@@ -373,7 +364,7 @@ USAGE
print ("----------------------")
for name in x393_mem.X393Mem.__dict__:
if hasattr((x393_mem.X393Mem.__dict__[name]), '__call__') and not (name[0]=='_'):
func_args=x393_mem.X393Mem.__dict__[name].func_code.co_varnames[1:x393_mem.X393Mem.__dict__[name].func_code.co_argcount]
func_args=x393_mem.X393Mem.__dict__[name].__code__.co_varnames[1:x393_mem.X393Mem.__dict__[name].__code__.co_argcount]
print (name+": "+str(func_args))
extractTasks(x393_mem.X393Mem,x393mem)
extractTasks(x393_utils.X393Utils, x393utils)
......@@ -443,7 +434,8 @@ USAGE
[], # potential_writers,
[]) # potential_errs,
if (not args.socket_port) and (sys.stdin in ready_to_read):
line=raw_input()
# line=raw_input()#python2
input()
# print ("stdin: ", line)
elif socket_conn in ready_to_read:
try:
......@@ -460,9 +452,9 @@ USAGE
continue
else: # No sockets, just command line input
if (not args.socket_port):
line=raw_input(prompt)
# line=raw_input(prompt) #python2
line=input(prompt)
# line=raw_input('x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))).strip()
line=line.strip() # maybe also remove comment?
# Process command, return result to a socket if it was a socket, not stdin
......@@ -541,8 +533,8 @@ USAGE
print('=== %s ==='%name)
print('defined in %s.%s, %s: %d)'%(str(callableTasks[name]['inst'].__class__.__module__),
callableTasks[name]['inst'].__class__.__name__,
callableTasks[name]['func'].func_code.co_filename,
callableTasks[name]['func'].func_code.co_firstlineno
callableTasks[name]['func'].__code__.co_filename,
callableTasks[name]['func'].__code__.co_firstlineno
))
sFuncArgs=getFuncArgsString(name)
docs=callableTasks[name]['docs']
......@@ -588,14 +580,15 @@ USAGE
print(" 'defines' command accepts regular expression as a second parameter to filter the list")
elif (lineList[0] == 'pydev_predefines'):
predefines=""
for k,v in ivp.parsToDict(parameters).items():
# for k,v in ivp.parsToDict(parameters).items():
for k,v in list(sorted(ivp.parsToDict(parameters).items(), key=lambda item:item[0])):
typ=str(type(v))
typ=typ[typ.find("'")+1:typ.rfind("'")]
if "None" in typ:
typ="None"
predefines += "%s = %s\n"%(k,typ)
# print ("%s = %s"%(k,typ))
vrlg_path=vrlg.__dict__["init_vars"].func_code.co_filename
vrlg_path=vrlg.__dict__["init_vars"].__code__.co_filename
# print ("vrlg path: %s"%(vrlg_path))
try:
magic="#### PyDev predefines"
......@@ -672,4 +665,4 @@ if __name__ == "__main__":
stats.print_stats()
statsfile.close()
sys.exit(0)
sys.exit(main())
\ No newline at end of file
sys.exit(main())
#!/bin/bash
# Updates vrlg.py to include predefines for pydev. Needed when new parameters are added to the Verilog header files
./test_mcntrl.py @cargs_test <<< $'pydev_predefines\nexit\n'
from __future__ import print_function
from __future__ import division
'''
# Copyright (C) 2015, Elphel.inc.
# Methods that mimic Verilog tasks used for simulation
......@@ -57,7 +59,7 @@ def concat(items):
width=0
for vw in reversed(items):
v=vw[0]
if not isinstance(v,(int,long)):
if not isinstance(v,(int,)):
if v:
v=1 # So True/False will also work, not just 0/1
else:
......@@ -151,7 +153,7 @@ def checkIntArgs(names,var_dict):
v=var_dict[name]
except:
raise Exception("ERROR: '%s' is not among %s"%(name,str(var_dict.keys())))
if not isinstance(v,(int,long)):
if not isinstance(v,(int,)):
print ("Expected an integer for '%s', got '%s"%(name,v))
try:
d=int(v,16)
......@@ -207,7 +209,7 @@ def combine_delay(dly):
try:
if isinstance(dly,float):
dly=int(dly+0.5)
return ((dly/NUM_FINE_STEPS)<<3)+(dly%NUM_FINE_STEPS)
return ((dly//NUM_FINE_STEPS)<<3)+(dly%NUM_FINE_STEPS)
except:
return None
......
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from __future__ import print_function
from __future__ import division
'''
# Copyright (C) 2015, Elphel.inc.
# Methods that mimic Verilog tasks used for simulation
......
......@@ -183,9 +183,11 @@ class X393Camsync(object):
self.set_camsync_period (SYNC_BIT_LENGTH) #set (bit_length -1) (should be 2..255), not the period
if not isinstance(camsync_delay,list) or isinstance(camsync_delay,tuple):
camsync_delay = (camsync_delay, camsync_delay, camsync_delay, camsync_delay)
print ("camsync_delay=",camsync_delay)
for i, dly in enumerate (camsync_delay):
if not dly is None:
self.set_camsync_delay(sub_chn = i, delay = dly)
print ("set_camsync_delay(",i, dly,")")
if not camsync_period is None:
self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set
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......@@ -116,7 +116,7 @@ class X393CmprsAfi(object):
else:
return self.x393_mem.read_mem(addr)
if isinstance(port_afi, (unicode,str)):
if isinstance(port_afi, (str,)):
data_file = port_afi%channel # for simulated mode
ba_data=bytearray()
try:
......
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......@@ -933,13 +933,16 @@ class X393Jpeg(object):
circbuf_len = x393_sens_cmprs.GLBL_CIRCBUF_ENDS[channel] - x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel],
verbose = verbose)
if verbose > 2 :
if verbose > 0: # 2 :
print ("meta = ",meta)
if verbose > 1 :
for s in meta["segments"]:
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
if "@" in file_path:
fts=("%f"%(meta["timestamp"])).replace(".","_")
try:
fts=("%f"%(meta["timestamp"])).replace(".","_")
except:
fts=str(channel)
file_path=file_path[:file_path.rindex('@')]+fts+file_path[file_path.rindex('@')+1:] #replacing '@'
with open (server_root+file_path, "w+b") as bf:
bf.write(jpeg_data["header"])
......
from __future__ import division
from __future__ import print_function
'''
# Copyright (C) 2015, Elphel.inc.
......@@ -236,7 +237,7 @@ class X393LMA(object):
isNone=np.isnan
# print ("using np.isnan")
# print("filtered=",filtered)
n=len(v)/32
n=len(v)//32
if 'A' in showMode.upper():
av=[]
for dly in range(n):
......@@ -880,7 +881,7 @@ class X393LMA(object):
@return 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
each element being either None, or a list of 3 best DQ delay values for the DQS delay (some mey be None too)
"""
if not isinstance(lane,(int, long)): # ignore content, process both lanes
if not isinstance(lane,(int,)): # ignore content, process both lanes
lane_rslt=[]
numLanes=2
parametersKey='parameters'
......@@ -1709,7 +1710,7 @@ class X393LMA(object):
print ("SX=",SX)
return minVal+bin_size_ps*(SX+0.5) # ps
if not isinstance(lane,(int, long)): # ignore content, process both lanes
if not isinstance(lane,(int,)): # ignore content, process both lanes
rslt_names=("dqs_optimal_ps","dqs_phase","dqs_phase_multi","dqs_phase_err","dqs_min_max_periods")
rslt= {}
for name in rslt_names:
......
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