...
 
Commits (18)
00 e8 01 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 01
00 00 e8 01 00 e8 01 00
00 00 00 00 00 00 01 01
00 00 04 00 00 55 00 0c
02 00 00 00 00 00 00 00
00 00 00 00 00 80 00 00
00 7e 80 9b 00 03 00 00
00 00 00 00 00 00 00 00
00 00 00 ff 60 88 88 88
60 60 40 60 60 60 60 40
40 40 40 60 60 60 00 00
00 00 00 00 00 00 00 ff
......@@ -678,6 +678,21 @@ class X393Sensor(object):
addr = 0,
data = ((reg_addr16 & 0xffff) << 16) | (reg_data16 & 0xffff) )
def write_sensor_spi_reg(self,
num_sensor,
reg_addr7,
reg_data8):
"""
Write spi register in immediate mode
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
@param reg_addr7 - 7-bit register address
@param reg_data8 - 8-bit data to write to sensor register
"""
self.write_sensor_i2c (num_sensor = num_sensor,
rel_addr = True,
addr = 0,
data = ( ((0x9000) << 16) | ( (reg_addr7 & 0x7f) << 8 ) | (reg_data8 & 0xff) ) )
def write_sensor_i2c (self,
num_sensor,
rel_addr,
......
......@@ -283,6 +283,56 @@ module sensor_i2c#(
.rq (status_rq), // output
.start (status_start) // input
);
`ifdef SENSOR_SPI
wire pin_spi_out;
wire pin_spi_in;
wire pin_spi_en;
wire pin_spi_reset;
wire pin_spi_clk;
reg read_spi_fifo;
reg spi_rd_en;
reg spi_wr_en;
wire valid_spi;
wire [31:0] data_spi;
wire spi_ready;
wire [7:0] data_from_spi;
reg spi_wr_fifo_en;
reg spi_pre_wr_fifo_en;
always @ (posedge mclk) begin
if (spi_wr_fifo_en) spi_wr_fifo_en <= 1'b0;
if (mrst) begin
spi_wr_fifo_en <= 1'b0;
spi_pre_wr_fifo_en <= 1'b0;
end
else if (spi_rd_en) spi_pre_wr_fifo_en <= 1'b1;
else if (spi_ready && spi_pre_wr_fifo_en) begin spi_pre_wr_fifo_en <= 1'b0; spi_wr_fifo_en <= 1'b1; end
end
fifo_same_clock #(
.DATA_WIDTH(8),
.DATA_DEPTH(4)
) fifo_same_clock_spi_rdata_i (
.rst (1'b0), // input
.clk (mclk), // input
.sync_rst (mrst), // input
.we (spi_wr_fifo_en), // input
.re (i2c_fifo_rd), // input
.data_in (data_from_spi), // input[7:0]
.data_out (i2c_fifo_dout), // output[7:0]
.nempty (i2c_fifo_nempty), // output
.half_full () // output reg
);
`else
fifo_same_clock #(
.DATA_WIDTH(8),
.DATA_DEPTH(4)
......@@ -297,6 +347,9 @@ module sensor_i2c#(
.nempty (i2c_fifo_nempty), // output
.half_full () // output reg
);
`endif
always @ (posedge mclk) begin
wr_full_r <= wr_full_w; // write buffer is almost full
......@@ -475,7 +528,74 @@ module sensor_i2c#(
.rvalid (i2c_rvalid) // output
);
`ifdef SENSOR_SPI
always @ (posedge mclk) begin
if (spi_wr_en) spi_wr_en <= 0;
if (spi_rd_en) spi_rd_en <= 0;
if (mrst) begin
read_spi_fifo <= 0;
spi_wr_en <= 0;
spi_rd_en <= 0;
end
else if (read_spi_fifo) read_spi_fifo <= 0;
else if ( valid_spi )
case ( data_spi[31:16] )
16'h9000 : if (spi_ready) begin spi_wr_en <= 1; read_spi_fifo <= 1; end
16'h9100 : if (spi_ready) begin spi_rd_en <= 1; read_spi_fifo <= 1; end
default: read_spi_fifo <= 1;
endcase
end
simul_fifo
#(
.WIDTH(32),
.DEPTH(64)
)simmul_fifo_i(
.clk(mclk),
.reset(mrst),
.data_in(di_r),
.load(i2c_cmd_we),
.input_ready(), //input ready to load
.data_out(data_spi),
.valid(valid_spi),
.ready(read_spi_fifo));
sensor_spi_io sensor_spi_io_i
(
.clk0(mclk), //clock 10-40MHz CMV300
.reset(mrst), //reset, active high
.addr(data_spi[14:8]), //spi address
.rd_en(spi_rd_en), //read from sensor enable, one clock period input signal
.wr_en(spi_wr_en), //write to sensor enable, one clock period input signal
.wr_data(data_spi[7:0]), //data to spi address be write
.reg_data(data_from_spi), //data from spi address will read
.spi_ready(spi_ready), //spi available for command
.pin_spi_out(pin_spi_out), //SPI interface pin: data out, direction from sensor to FPGA
.pin_spi_in(pin_spi_in), //SPI interface pin: data in, direction from FPGA to sensor
.pin_spi_en(pin_spi_en), //SPI interface pin: data enable, direction from FPGA to sensor
.pin_spi_reset(pin_spi_reset), //SPI interface pin: data reset, direction from FPGA to sensor
.pin_spi_clk(pin_spi_clk) //SPI interface pin: data clock, direction from FPGA to sensor
);
simul_sensor_spi # (
.SENSOR_IMAGE_TYPE ("NORM"),
.SENSOR_TYPE ("CMV300")
) simul_sensor_spi_i (
.pin_spi_out(pin_spi_out), //SPI interface pin: data out, direction from sensor to FPGA
.pin_spi_in(pin_spi_in), //SPI interface pin: data in, direction from FPGA to sensor
.pin_spi_en(pin_spi_en), //SPI interface pin: data enable, direction from FPGA to sensor
.pin_spi_reset(pin_spi_reset), //SPI interface pin: data reset, direction from FPGA to sensor
.pin_spi_clk(pin_spi_clk) //SPI interface pin: data clock, direction from FPGA to sensor
);
`else
ram_var_w_var_r #(
.REGISTERS(1), // try to delay i2c_byte_start by one more cycle
......@@ -494,5 +614,8 @@ module sensor_i2c#(
.data_in (di_r) // input[31:0]
);
`endif
endmodule
/*!
* <b>Module:</b>sensor_spi_io
* @file sensor_spi_io.v
* @date 2017-05-17
* @author Raimundas Bastys
*
* @brief module to data in/out from/to CMV300 spi port, tested s6
*
* @copyright Copyright (c) 2017 Raimundas Bastys
*
* <b>License:</b>
*
* sensor_spi_io.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sensor_spi_io.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
//v0.0 working on s6lx4-3 10-40MHz clock with PCB CS01, not passing to datasheet CMV300 - extra clock to end spi enable period
//v0.1 change ODDR2(s6) to ODDR(zynq)
`timescale 1ns/1ps
module sensor_spi_io
(
input clk0, //clock 10-40MHz CMV300
input reset, //reset, active high
input [6:0] addr, //spi address
input rd_en, //read from sensor enable, one clock period input signal
input wr_en, //write to sensor enable, one clock period input signal
input [7:0] wr_data, //data to spi address be write
output reg [7:0] reg_data, //data from spi address will read
output reg spi_ready, //spi available for command
input pin_spi_out, //SPI interface pin: data out, direction from sensor to FPGA
output reg pin_spi_in, //SPI interface pin: data in, direction from FPGA to sensor
output reg pin_spi_en, //SPI interface pin: data enable, direction from FPGA to sensor
output pin_spi_reset, //SPI interface pin: data reset, direction from FPGA to sensor
output pin_spi_clk //SPI interface pin: data clock, direction from FPGA to sensor
);
reg [7:0] sfst;
reg [3:0] sfst_ciklu;
reg [15:0] spi_word_rd;
reg [15:0] spi_word_wr;
reg read_bit;
reg [3:0] sfst_bits;
reg [7:0] sfst_byte;
assign pin_spi_reset = !reset;
`define S_FST_000 8'h00
`define S_FST_WR0 8'h01
`define S_FST_WR1 8'h02
`define S_FST_RD0 8'h03
`define S_FST_RD1 8'h04
`define S_FST_END 8'h05
always @ ( posedge clk0 ) begin
if ( reset ) begin
sfst <= `S_FST_000;
pin_spi_en <= 1'b0;
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
read_bit <= 1'b0;
sfst_bits[3:0] <= 4'b0000;
sfst_byte[7:0] <= 8'h00;
reg_data[7:0] <= 8'h00;
spi_ready <= 1'b1;
end else begin
case ( sfst )
`S_FST_000 : begin
pin_spi_en <= 1'b0;
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
read_bit <= 1'b0;
spi_word_rd[15:0] <= {1'b0, addr[6:0], 8'h00};
spi_word_wr[15:0] <= {1'b1, addr[6:0], wr_data[7:0]};
if (rd_en) begin
spi_ready <= 1'b0;
sfst <= `S_FST_RD0;
end
if (wr_en) begin
spi_ready <= 1'b0;
sfst <= `S_FST_WR0;
end
end
`S_FST_RD0 : begin
pin_spi_en <= 1'b0;
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
read_bit <= 1'b0;
sfst <= `S_FST_RD1;
end
`S_FST_RD1 : begin
pin_spi_en <= 1'b1;
read_bit <= 1'b0;
pin_spi_in <= spi_word_rd[15];
spi_word_rd[15:1] <= spi_word_rd[14:0];
if ( sfst_ciklu[3:0] == 4'b0000) begin
read_bit <= 1'b0;
sfst <= `S_FST_END;
end else if ( sfst_ciklu[3:0] == 4'h7) begin //begin read from CMV300
read_bit <= 1'b1;
sfst_ciklu[3:0] <= sfst_ciklu[3:0] -1 ;
sfst <= `S_FST_RD1;
end else begin
read_bit <= 1'b0;
sfst_ciklu[3:0] <= sfst_ciklu[3:0] -1 ;
sfst <= `S_FST_RD1;
end
end
`S_FST_WR0 : begin
pin_spi_en <= 1'b0;
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
sfst <= `S_FST_WR1;
end
`S_FST_WR1 : begin
pin_spi_en <= 1'b1;
pin_spi_in <= spi_word_wr[15];
spi_word_wr[15:1] <= spi_word_wr[14:0];
if ( sfst_ciklu[3:0] == 4'b0000) begin
sfst <= `S_FST_END;
end else begin
sfst_ciklu[3:0] <= sfst_ciklu[3:0] -1 ;
sfst <= `S_FST_WR1;
end
end
`S_FST_END : begin
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
read_bit <= 1'b0;
spi_ready <= 1'b1;
sfst <= `S_FST_000;
end
endcase
if ( read_bit ) begin
sfst_bits[3:0] <= 4'h7;
sfst_byte[7:0] <= {sfst_byte[6:0], pin_spi_out};
end
if ( sfst_bits[3:0] == 4'h0 ) begin
reg_data[7:0] <= sfst_byte[7:0];
end else begin
sfst_byte[7:0] <= {sfst_byte[6:0], pin_spi_out};
sfst_bits[3:0] <= sfst_bits[3:0] - 1;
end
end //if
end //always
ODDR #(
// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_sens (
.Q(pin_spi_clk), // 1-bit DDR output data
.C(clk0), // 1-bit clock input
// .C0(clk0), // 1-bit clock input
// .C1(!clk0), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
// .D0(1'b0), // 1-bit data input (associated with C0)
// .D1(1'b1), // 1-bit data input (associated with C1)
.D1(1'b0), // 1-bit data input
.D2(1'b1), // 1-bit data input
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
endmodule // sensor_spi_io
/*!
* <b>Module:</b> simul_sensor_spi
* @file simul_sensor_spi.v
* @date 2017-09-04
* @author Raimundas Bastys
*
* @brief Generate spi sensor data
*
* @copyright Copyright (c) 2017 Raimundas Bastys
*
* <b>License </b>
*
* simul_sensor_spi.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_sensor_spi.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_sensor_spi # (
parameter SENSOR_IMAGE_TYPE = "NORM",
parameter SENSOR_TYPE = "CMV300",
parameter tSPI = 4 //time data from clock rise front
) (
output pin_spi_out, //SPI interface pin: data out, direction from sensor to FPGA
input pin_spi_in, //SPI interface pin: data in, direction from FPGA to sensor
input pin_spi_en, //SPI interface pin: data enable, direction from FPGA to sensor
input pin_spi_reset, //SPI interface pin: data reset, direction from FPGA to sensor
input pin_spi_clk //SPI interface pin: data clock, direction from FPGA to sensor
);
reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [7:0] sensor_spi_reg[0:127]; // sensor SPI registers
reg spi_out;
wire clk;
wire reset; //active high
reg [7:0] sfst;
reg [6:0] reg_addr;
reg [2:0] ciklu_addr;
reg [7:0] reg_wr;
assign pin_spi_out=spi_out;
assign clk = pin_spi_clk;
assign reset = !pin_spi_reset || !pin_spi_en;
`ifndef ROOTPATH
`include "IVERILOG_INCLUDE.v"// SuppressThisWarning VEditor - maybe not used
`ifndef ROOTPATH
`define ROOTPATH "."
`endif
`endif
initial begin
$display ("sensor parameters");
$display (" -- sensor = %s",SENSOR_TYPE);
$display (" -- image type = %s",SENSOR_IMAGE_TYPE);
if (SENSOR_IMAGE_TYPE == "NORM") $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "RUN1") $readmemh({`ROOTPATH,"/input_data/sensor_run1.dat"},sensor_data);
else begin
$display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
$readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
end
if (SENSOR_TYPE == "CMV300") $readmemh({`ROOTPATH,"/input_data/sensor_spi_reg.dat"},sensor_spi_reg);
else begin
$display ("WARNING: Unrecognized sensor :'%s', using default 'CMV300': input_data/sensor_spi_reg.dat",SENSOR_TYPE);
$readmemh({`ROOTPATH,"/input_data/sensor_spi_reg.dat"},sensor_spi_reg);
end
end
`define S_FST_00000 8'h00
`define S_FST_WR_A0 8'h01
`define S_FST_WR_D0 8'h02
`define S_FST_RD_A0 8'h03
`define S_FST_RD_D0 8'h04
always @ ( posedge clk or posedge reset ) begin
if ( reset ) begin
sfst <= `S_FST_00000;
reg_addr[6:0] <= 0;
ciklu_addr[2:0] <= 3'b110;
reg_wr <= 0;
end else begin
case ( sfst )
`S_FST_00000 : begin
ciklu_addr[2:0] <= 3'b110; //6 addr bit
if (pin_spi_in)
sfst <= `S_FST_WR_A0;
else
sfst <= `S_FST_RD_A0;
end
`S_FST_RD_A0 : begin
reg_addr[ciklu_addr] <= pin_spi_in;
if ( ciklu_addr[2:0] == 3'b000) begin
ciklu_addr[2:0] <= 3'b111; //7 data bit
sfst <= `S_FST_RD_D0;
end else
ciklu_addr[2:0] <= ciklu_addr[2:0] - 1;
end
`S_FST_RD_D0 : begin
// #tSPI spi_out <= sensor_spi_reg[reg_addr[6:0]][ciklu_addr[2:0]];
if ( ciklu_addr[2:0] == 3'b000)
sfst <= `S_FST_00000;
else
ciklu_addr[2:0] <= ciklu_addr[2:0] - 1;
end
`S_FST_WR_A0 : begin
reg_addr[ciklu_addr] <= pin_spi_in;
if ( ciklu_addr[2:0] == 3'b000) begin
ciklu_addr[2:0] <= 3'b111;//7 data bit
sfst <= `S_FST_WR_D0;
end else
ciklu_addr[2:0] <= ciklu_addr[2:0] - 1;
end
`S_FST_WR_D0 : begin
reg_wr[ciklu_addr[2:0]] <= pin_spi_in;
if ( ciklu_addr[2:0] == 3'b000) begin
sensor_spi_reg[reg_addr[6:0]][7:0] <= {reg_wr[7:1], pin_spi_in};
sfst <= `S_FST_00000;
end else
ciklu_addr[2:0] <= ciklu_addr[2:0] - 1;
end
endcase
end //if
end //always
always @ ( negedge clk or posedge reset ) begin
if ( reset ) begin
spi_out <= 1'b0;
end else begin
case ( sfst )
`S_FST_RD_D0 : begin
spi_out <= sensor_spi_reg[reg_addr[6:0]][ciklu_addr[2:0]];
end
endcase
end //if
end //always
endmodule
......@@ -49,6 +49,7 @@
`define DEBUG_COMPRESSOR_SCRAMBLE
`define DEBUG_DCT1D // undefine after debugging is over
// `define USE_OLD_DCT
`define SENSOR_SPI //define if used SPI sensor CMV300
// Parameters from x393_sata project
`define USE_DRP
......@@ -215,4 +216,4 @@
`undef def_scanline_chn15
`define def_tiled_chn15
`endif
\ No newline at end of file
/*******************************************************************************
* Module: x393_testbench_spi
* Date:2017-09-07
* Author: Raimundas Bastys
* Description: testbench for the SPI modules simulation
*
* Copyright (c) 2015 Elphel, Inc.
* x393_testbench_spi.tf is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_testbench_spi.tf is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
`define SAME_SENSOR_DATA 1
//`undef SAME_SENSOR_DATA
`define COMPRESS_SINGLE
`define USE_CMPRS_IRQ
`define USE_FRAME_SEQ_IRQ
//`define use200Mhz 1
//`define DEBUG_FIFO 1
`undef WAIT_MRS
`define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays)
`define READBACK_DELAYS 1
//`define TEST_MEMBRIDGE 1 // was not set
`undef TEST_MEMBRIDGE // was not set
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
// Disabled already passed test to speedup simulation
//`define TEST_WRITE_LEVELLING 1
//`define TEST_READ_PATTERN 1
//`define TEST_WRITE_BLOCK 1
//`define TEST_READ_BLOCK 1
//`define TEST_SCANLINE_WRITE
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ
`define TEST_READ_SHOW 1
//`define TEST_TILED_WRITE 1
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_TILED_READ 1
//`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1
//`define TEST_AFI_WRITE 1
//`define TEST_AFI_READ 1
`define TEST_SENSOR 0
*/
module x393_testbench_spi #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
`include "includes/x393_simulation_parameters.vh"
)(
);
`ifdef IVERILOG
// $display("IVERILOG is defined");
`ifdef NON_VDT_ENVIROMENT
parameter fstname="x393.fst";
`else
`include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
`else // IVERILOG
// $display("IVERILOG is not defined");
`ifdef CVC
`ifdef NON_VDT_ENVIROMENT
parameter fstname = "x393.fst";
`else // NON_VDT_ENVIROMENT
`include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
`else
parameter fstname = "x393.fst";
`endif // CVC
`endif // IVERILOG
reg RST_CLEAN = 1;
wire CLK;
reg reset;
wire [7:0] reg_data;
reg [7:0] wr_data;
reg wr_en = 0;
reg rd_en = 0;
reg [6:0] addr;
wire spi_ready;
// Sensor signals - as on sensor pads
wire [3:0] PX1_LANE_P; // from sensor to FPGA
wire [3:0] PX1_LANE_N; // from sensor to FPGA
wire PX1_CLK_P; // from sensor to FPGA
wire PX1_CLK_N; // from sensor to FPGA
wire PX1_CTRL_P; // from sensor to FPGA
wire PX1_CTRL_N; // from sensor to FPGA
wire PX1_MRST; // from FPGA to sensor
wire PX1_FR_RQ; // from FPGA to sensor
wire PX1_EXP1; // from FPGA to sensor
wire PX1_EXP2; // from FPGA to sensor
wire PX1_SPI_EN; // from FPGA to sensor
wire PX1_SCL; // from FPGA to sensor
wire PX1_SPI_OUT; // from sensor to FPGA
wire PX1_MCLK; // from FPGA to sensor, sensor input clock
wire PX1_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
// Sensor signals - as on FPGA pads
wire [ 7:0] sns1_dp; // inout[7:0] {PX1_SPI_EN, PX1_EXP2, PX1_FR_RQ, PX1_CTRL_P, PX1_LANE_P[3:0]}
wire [ 7:0] sns1_dn; // inout[7:0] {PX1_MCLK_PRE, PX1_MRST, PX1_EXP1, PX1_CTRL_N, PX1_LANE_N[3:0]}
wire sns1_clkp; // inout PX1_CLK_P
wire sns1_clkn; // inout PX1_CLK_N
wire sns1_scl; // inout PX_SCL
wire sns1_sda; // inout PX_SDA, PX_SPI_I
wire sns1_ctl; // inout TCK, PX_SPI_O
wire sns1_pg; // inout SENSPGM
//
assign sns1_dp[3:0] = PX1_LANE_P[3:0]; // from sensor to FPGA
assign sns1_dn[3:0] = PX1_LANE_N[3:0]; // from sensor to FPGA
assign sns1_clkp = PX1_CLK_P; // from sensor to FPGA
assign sns1_clkn = PX1_CLK_N; // from sensor to FPGA
assign sns1_dp[4] = PX1_CTRL_P; // from sensor to FPGA
assign sns1_dn[4] = PX1_CTRL_N; // from sensor to FPGA
assign PX1_FR_RQ = sns1_dp[5]; // from FPGA to sensor
assign PX1_EXP1 = sns1_dn[5]; // from FPGA to sensor
assign PX1_EXP2 = sns1_dp[6]; // from FPGA to sensor
assign PX1_MRST = sns1_dn[6]; // from FPGA to sensor
assign PX1_SPI_EN = sns1_dp[7]; // from FPGA to sensor
assign PX1_MCLK_PRE = sns1_dn[7]; // from FPGA to sensor
assign PX1_SCL = sns1_scl; // from FPGA to sensor
// sns1_sda // inout FPGA - sensor, i2c data and SPI input form FPGA to sensor
assign sns1_ctl = PX1_SPI_OUT; // from sensor to FPGA
// modules
sensor_spi_io sensor_spi_io_i
(
.clk0(CLK), //clock 10-40MHz CMV300
.reset(reset), //reset, active high
.addr(addr), //spi address
.rd_en(rd_en), //read from sensor enable, one clock period input signal
.wr_en(wr_en), //write to sensor enable, one clock period input signal
.wr_data(wr_data), //data to spi address be write
.reg_data(reg_data), //data from spi address will read
.spi_ready(spi_ready), //spi available for command
.pin_spi_out(sns1_ctl), //SPI interface pin: data out, direction from sensor to FPGA
.pin_spi_in(sns1_sda), //SPI interface pin: data in, direction from FPGA to sensor
.pin_spi_en(sns1_dp[7]), //SPI interface pin: data enable, direction from FPGA to sensor
.pin_spi_reset(sns1_dn[6]), //SPI interface pin: data reset, direction from FPGA to sensor
.pin_spi_clk(PX1_MCLK) //SPI interface pin: data clock, direction from FPGA to sensor
);
// Simulation modules
simul_clk_single #(
.PERIOD(25)
) simul_clk_i (
.rst(1'b0),
.clk(CLK)
);
simul_sensor_spi # (
.SENSOR_IMAGE_TYPE ("NORM"),
.SENSOR_TYPE ("CMV300")
) simul_sensor_spi_i (
.pin_spi_out(PX1_SPI_OUT), //SPI interface pin: data out, direction from sensor to FPGA
.pin_spi_in(sns1_sda), //SPI interface pin: data in, direction from FPGA to sensor
.pin_spi_en(PX1_SPI_EN), //SPI interface pin: data enable, direction from FPGA to sensor
.pin_spi_reset(PX1_MRST), //SPI interface pin: data reset, direction from FPGA to sensor
.pin_spi_clk(PX1_MCLK) //SPI interface pin: data clock, direction from FPGA to sensor
);
task read_spi;
input [6:0] adresas;
begin
addr[6:0] <= adresas [6:0];
rd_en <= 1'b1;
wait (CLK);
wait (!CLK);
wait (CLK);
rd_en <= 1'b0;
wait (!CLK && spi_ready);
wait (CLK);
wait (!CLK);
end
endtask
task write_spi;
input [6:0] adresas;
input [7:0] write_data;
begin
addr[6:0] <= adresas [6:0];
wr_data[7:0] <= write_data [7:0];
wr_en <= 1'b1;
wait (CLK);
wait (!CLK);
wait (CLK);
wr_en <= 1'b0;
wait (!CLK && spi_ready);
wait (CLK);
wait (!CLK);
end
endtask
task all_regs_spi; //task destroy original registers values
integer i;
reg [6:0] adresas;
reg ok;
begin
ok = 1;
adresas = 0;
for (i=0; i<128; i=i+1) begin
read_spi(adresas);
$display("SPI %d reg - %d =====", addr, reg_data);
adresas = adresas + 1;
end
adresas = 0;
for (i=0; i<128; i=i+1) begin
write_spi(adresas,adresas[6:0] + 8'h80);
adresas = adresas + 1;
end
adresas = 0;
for (i=0; i<128; i=i+1) begin
read_spi(adresas);
if ( addr[6:0] + 8'h80 != reg_data[7:0])
ok = 0;
adresas = adresas + 1;
end
$display("");
if ( ok == 0)
$display("SPI registers self write-read - ERROR ===== original registers values destroyed");
else
$display("SPI registers self write-read - OK ===== original registers values destroyed");
$display("");
end
endtask
initial begin
`ifdef IVERILOG
$display("IVERILOG is defined");
`else
$display("IVERILOG is not defined");
`endif
`ifdef ICARUS
$display("ICARUS is defined");
`else
$display("ICARUS is not defined");
`endif
$dumpfile(fstname);
$dumpvars(0,x393_testbench_spi);
RST_CLEAN = 1;
reset = 1'bx;
#500;
reset = 1'b1;
#9000; // same as glbl
repeat (20) @(posedge CLK) ;
reset = 1'b0;
@(posedge CLK) ;
RST_CLEAN = 0;
@(posedge CLK) ;
$display("original SPI registers:");
$display("");
all_regs_spi; //task destroy original registers values
#15000;
$display("normal finish testbench");
$finish;
end
// protect from never end
initial begin
#2000000;
$display("finish testbench (before end)");
$finish;
end
endmodule