...
 
Commits (71)
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>x393</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.python.pydev.PyDevBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.elphel.vdt.veditor.simulateBuilder</name>
<arguments>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>
<value>echo &apos;Clean&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>
<value>0</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>
<value>echo &apos;No Build Configuration Specified&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>
<value>true</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>
<value>Default</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>
<value></value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>
<value></value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.elphel.vdt.veditor.HdlNature</nature>
<nature>org.python.pydev.pythonNature</nature>
</natures>
</projectDescription>
cocotb_@_COCOTB_DEBUG=false
cocotb_@_CocotbDutTopFile=cocotb/x393_dut.v
cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->
cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_@_GrepFindErr=error|ERROR
cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING
cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)
cocotb_@_SaveLogsPreprocessor=true
cocotb_@_SaveLogsSimulator=true
com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->cocotb_@_GrepFindErrWarn<-@\#\#@->cocotb_@_SaveLogsPreprocessor<-@\#\#@->cocotb_@_SaveLogsSimulator<-@\#\#@->cocotb_@_GrepFindErr<-@\#\#@->cocotb_@_PatternInfo<-@\#\#@->cocotb_@_COCOTB_DEBUG<-@\#\#@->
com.elphel.store.version.cocotb=0.8
eclipse.preferences.version=1
......@@ -49,17 +49,21 @@ x393_testbench03_01.sav
simulation_data/*.dat
simulation_data/*.jpeg
#these two project files are now in .eclipse_project_setup directory
.project
.pydevproject
py393/.project
/.project
/.pydevproject
/.settings
#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
workingSet.psf
/workingSet.psf
*.fst
cocotb/Makefile
cocotb/sim_build
cocotb/results.xml
*.directory
html.tar.gz
latex
bitbake-logs
sysroots
image
/latex
/bitbake-logs
/sysroots
/image
/scripts
FPGA_project_@_DUTTopFile=cocotb/x393_dut.v
FPGA_project_@_DUTTopModule=x393_dut
FPGA_project_@_ImplementationTopFile=x393.v
FPGA_project_@_SimulationTopFile=x393_testbench03.tf
FPGA_project_@_SimulationTopModule=x393_testbench03
FPGA_project_@_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
VivadoBitstream_@_rawfile=x393_parallel
com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
VivadoOpt_@_SkipSnapshotOpt=true
com.elphel.store.context.VivadoOpt=VivadoOpt_@_SkipSnapshotOpt<-@\#\#@->
eclipse.preferences.version=1
VivadoOptPhys_@_SkipSnapshotOptPhys=true
com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_@_SkipSnapshotOptPhys<-@\#\#@->
eclipse.preferences.version=1
VivadoOptPower_@_SkipSnapshotOptPower=true
com.elphel.store.context.VivadoOptPower=VivadoOptPower_@_SkipSnapshotOptPower<-@\#\#@->
eclipse.preferences.version=1
VivadoPlace_@_SkipSnapshotPlace=true
VivadoPlace_@_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->
eclipse.preferences.version=1
VivadoRoute_@_SkipSnapshotRoute=true
VivadoRoute_@_directive_route=MoreGlobalIterations
com.elphel.store.context.VivadoRoute=VivadoRoute_@_SkipSnapshotRoute<-@\#\#@->VivadoRoute_@_directive_route<-@\#\#@->
eclipse.preferences.version=1
VivadoSynthesis_@_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@->
VivadoSynthesis_@_MaxMsg=20000
VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_@_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
VivadoSynthesis_@_ResetProject=true
VivadoSynthesis_@_ShowInfo=true
VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_@_verbose=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_PreTCL<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_ResetProject<-@\#\#@->
com.elphel.store.version.VivadoSynthesis=1.1
eclipse.preferences.version=1
VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
VivadoTimingReportImplemented_@_DisableVivadoTiming=true
VivadoTimingReportImplemented_@_rawfile=
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_@_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@->
eclipse.preferences.version=1
VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
com.elphel.store.context.iverilog=iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_ShowWarnings<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1
iverilog_@_ExtraFiles=glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=x393_testbench04.sav
iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_@_SaveLogsPreprocessor=false
iverilog_@_SaveLogsSimulator=true
iverilog_@_ShowNoProblem=true
iverilog_@_ShowWarnings=false
iverilog_@_TopModulesOther=glbl<-@\#\#@->
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
eclipse.preferences.version=1
encoding//attic/gen_hist_test.py=utf-8
encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
encoding//py393/test_mcntrl.py=utf-8
encoding//py393/x393_i2c.py.test=utf-8
encoding//py393/x393_init_usb_hub.py=utf-8
This diff is collapsed.
......@@ -23,6 +23,7 @@ COMMAND_FILES = py393/hargs \
py393/hargs-auto \
py393/hargs-after \
py393/hargs-eyesis \
py393/hargs-hispi \
py393/hargs-post-par12 \
py393/hargs-power_par12 \
py393/hargs-power-eyesis \
......@@ -51,4 +52,3 @@ install:
clean:
@echo "make clean in x393"
\ No newline at end of file
......@@ -503,6 +503,7 @@ module histogram_saxi#(
);
ram_var_w_var_r #(
.COMMENT("histogram_saxi"),
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5),
......
......@@ -497,6 +497,7 @@ module mult_saxi_wr #(
generate
if (MULT_SAXI_HALF_BRAM)
ram18_var_w_var_r #(
.COMMENT("mult_saxi_wr_MULT_SAXI_HALF_BRAM"),
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5),
......@@ -515,6 +516,7 @@ module mult_saxi_wr #(
);
else
ram_var_w_var_r #(
.COMMENT("mult_saxi_wr_not_MULT_SAXI_HALF_BRAM"),
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5),
......
......@@ -120,6 +120,7 @@ module mult_saxi_wr_inbuf#(
generate
if (MULT_SAXI_HALF_BRAM_IN)
ram18_var_w_var_r #(
.COMMENT("mult_saxi_wr_inbuf_MULT_SAXI_HALF_BRAM_IN"),
.REGISTERS(1),
.LOG2WIDTH_WR(MULT_SAXI_WLOG),
.LOG2WIDTH_RD(5),
......@@ -138,6 +139,7 @@ module mult_saxi_wr_inbuf#(
);
else
ram_var_w_var_r #(
.COMMENT("mult_saxi_wr_inbuf_not_MULT_SAXI_HALF_BRAM_IN"),
.REGISTERS(1),
.LOG2WIDTH_WR(MULT_SAXI_WLOG),
.LOG2WIDTH_RD(5),
......
This diff is collapsed.
......@@ -418,14 +418,16 @@ module x393_dut#(
parameter PF_STRIPES=WOI_HEIGHT/PF_HEIGHT;
`else
parameter PF_HEIGHT=0; // SuppressThisWarning VEditor - not used
parameter FULL_HEIGHT=WOI_HEIGHT+4;
parameter PF_STRIPES=0; // SuppressThisWarning VEditor - not used
`endif
parameter WOI_MARGINS = 0; // 4;
parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK;
parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED
parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED
parameter TRIG_DELAY= 200; /// delay in sensor clock cycles // SuppressThisWarning VEditor - not used
parameter FULL_WIDTH= WOI_WIDTH+4;
parameter FULL_WIDTH= WOI_WIDTH + WOI_MARGINS;
parameter FULL_HEIGHT= WOI_HEIGHT + WOI_MARGINS;
// localparam SENSOR_MEMORY_WIDTH_BURSTS = (FULL_WIDTH + 15) >> 4;
// localparam SENSOR_MEMORY_MASK = (1 << (FRAME_WIDTH_ROUND_BITS-4)) -1;
// localparam SENSOR_MEMORY_FULL_WIDTH_BURSTS = (SENSOR_MEMORY_WIDTH_BURSTS + SENSOR_MEMORY_MASK) & (~SENSOR_MEMORY_MASK);
......@@ -670,22 +672,35 @@ module x393_dut#(
`else
//connect parallel12 sensor to sensor port 2 (all data rotated left by 1 bit)
assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
/// assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
/// assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
/// assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
/// assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
assign sns2_dp[6:1] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_HACT};
assign sns2_dn[6:0] = {PX2_D[11], PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_VACT, PX2_DCLK};
assign sns2_clkn = PX2_D[0]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[1]; // CNVCLK/TDO
//connect parallel12 sensor to sensor port 3 (all data rotated left by 2 bits
assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
/// assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
/// assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
/// assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
/// assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
assign sns3_dp[6:1] = {PX3_D[10], PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_HACT};
assign sns3_dn[6:0] = {PX3_D[11], PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_VACT, PX3_DCLK};
assign sns3_clkn = PX3_D[0]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[1]; // CNVCLK/TDO
//connect parallel12 sensor to sensor port 4 (all data rotated left by 3 bits
assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
/// assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
/// assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
/// assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
/// assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
assign sns4_dp[6:1] = {PX4_D[10], PX4_D[8], PX4_D[6], PX4_D[4], PX4_D[2], PX4_HACT};
assign sns4_dn[6:0] = {PX4_D[11], PX4_D[9], PX4_D[7], PX4_D[5], PX4_D[3], PX4_VACT, PX4_DCLK};
assign sns4_clkn = PX4_D[0]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[1]; // CNVCLK/TDO
`endif
`endif
......@@ -1552,6 +1567,40 @@ simul_axi_hp_wr #(
.clk_out (PX4_MCLK) // output
);
/* Instance template for module simul_lwir160x120_vospi */
wire lwir1_miso;
simul_lwir160x120_vospi #(
.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
.WINDOW_WIDTH (160),
.WINDOW_HEIGHT (120),
.TELEMETRY (2), // 1),
.FRAME_PERIOD (946969),
.FRAME_DELAY (100),
.MS_PERIOD (25) // 1us instead of 1 ms
) simul_lwir160x120_vospi_i (
.mclk (x393_i.ps7_i.SAXIHP0ACLK), // PX1_MCLK), // input temporarily made faster
.nrst ( PX1_MRST), // input
.sck ( 1'b0), // input
.ncs ( 1'b0), // inout
.miso ( lwir1_miso), // output
.telemetry_rev ( 16'h7654), // input[15:0]
.telemetry_status ( 32'h137f1248), // input[31:0]
.telemetry_srev (64'h0123456789abcdef), // input[63:0]
.telemetry_temp_counts ( 16'd59000), // input[15:0]
.telemetry_temp_kelvin ( 16'd29500), // input[15:0]
.telemetry_temp_last_kelvin ( 16'd29300), // input[15:0]
.telemetry_time_last_ms ( 32'h12345678), // input[31:0]
.telemetry_agc_roi_top ( 16'd0), // input[15:0]
.telemetry_agc_roi_left ( 16'd0), // input[15:0]
.telemetry_agc_roi_bottom ( 16'd119), // input[15:0]
.telemetry_agc_roi_right ( 16'd159), // input[15:0]
.telemetry_agc_high (16'd19200), // input[15:0]
.telemetry_agc_low ( 16'd200), // input[15:0]
.telemetry_video_format (32'haaaa5555) // input[31:0]
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE0),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
......@@ -1572,7 +1621,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (0) // was 1 SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1 SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(0)
) simul_sensor12bits_i (
.MCLK (PX1_MCLK), // input
.MRST (PX1_MRST), // input
......@@ -1611,7 +1661,9 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
.new_bayer (0), //SENSOR12BITS_NEW_BAYER) was 1
.EXTRA_PERIOD (50)
) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input
`ifdef DISABLE_SENSOR_2
......@@ -1653,7 +1705,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), // SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(100)
) simul_sensor12bits_3_i (
.MCLK (PX3_MCLK), // input
.MRST (PX3_MRST), // input
......@@ -1691,7 +1744,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0),// SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(120)
) simul_sensor12bits_4_i (
.MCLK (PX4_MCLK), // input
.MRST (PX4_MRST), // input
......
This diff is collapsed.
......@@ -66,7 +66,7 @@ module cmprs_buf_average#(
input [ 7:0] caddrw,
input cwe,
input [ 8:0] signed_c,
output [ 9:0] do, // [9:0] data out (4:2:0) (signed, average=0)
output [ 9:0] dout, // [9:0] data out (4:2:0) (signed, average=0)
// When is it valid?
output [ 8:0] avr, // [8:0] DC (average value) - RAM output, no register. For Y components 9'h080..9'h07f, for C - 9'h100..9'h0ff!
output dv, // out data valid (will go high for at least 64 cycles)
......@@ -170,7 +170,7 @@ module cmprs_buf_average#(
// assign output signals
assign avr = avr_r; // avermem[avr_ra[3:0]];
assign do = do_r;
assign dout = do_r;
assign tn[2:0] = raddr[8:6];
// component_num,component_color,component_first for different converters vs tn (1 bit per tn (0..5)
assign component_num[2:0]= {component_numsH[0],component_numsM[0],component_numsL[0]};
......
This diff is collapsed.
......@@ -45,7 +45,6 @@ module cmprs_frame_sync#(
parameter CMPRS_TIMEOUT= 1000 // mclk cycles
)(
// input rst,
input xclk, // global clock input, compressor single clock rate
input mclk, // global system/memory clock
input mrst, // @posedge mclk, sync reset
......@@ -88,7 +87,7 @@ module cmprs_frame_sync#(
output reg force_flush_long, // force flush (abort frame), can be any clock and may last until stuffer_done_mclk
// stuffer will re-clock and extract 0->1 transition
output stuffer_running_mclk,
output reading_frame,
output reading_frame, // @mclk
output frame_started_mclk // use to store frame number
);
/*
......@@ -101,8 +100,6 @@ module cmprs_frame_sync#(
TODO: Simplify logic: instead of frame_start_pend_r - copy frame_number_srtc @ vsync_late, and start frame if it is not reading,
in "run" mode, and frame_number_differ (in multi-frame mode)
*/
// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
// wire frame_started_mclk;
reg bonded_mode;
reg [5:0] frame_start_dst_r;
reg frame_start_pend_r; // postpone frame_start_dst if previous frame was still being read during vsync_late
......@@ -111,14 +108,12 @@ module cmprs_frame_sync#(
reg line_numbers_sync; // src unfinished line number is > this unfinished line number
reg reading_frame_r; // compressor is reading frame data (make sure input is done before starting next frame, otherwise make it a broken frame
// reg broken_frame;
reg aborted_frame;
reg stuffer_running_mclk_r;
reg [CMPRS_TIMEOUT_BITS-1:0] timeout;
reg cmprs_en_extend_r=0;
reg cmprs_en_d;
reg suspend_end; // suspend at the end of the current frame until frame number changes
// reg cmprs_en_xclk;
wire last_mb_started_mclk;
assign frame_start_dst = frame_start_dst_r[0];
assign cmprs_en_extend = cmprs_en_extend_r;
......@@ -126,9 +121,6 @@ module cmprs_frame_sync#(
assign stuffer_running_mclk = stuffer_running_mclk_r;
assign reading_frame = reading_frame_r;
// always @ (posedge xclk) begin
// cmprs_en_xclk <=cmprs_en;
// end
always @ (posedge mclk) begin
if (mrst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1;
......@@ -145,28 +137,18 @@ module cmprs_frame_sync#(
cmprs_en_d <= cmprs_en;
// broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;
if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0;
// else if (broken_frame || aborted_frame) force_flush_long <= 1;
else if (aborted_frame) force_flush_long <= 1;
// if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0;
// last_mb_start[2] is used as emergency turn off reading_frame if memory channel did not generate frame_done (i.e. wrong frame height)
// TODO: Consider the opposite - frame_done, but not got the last MB?
if (!cmprs_en || frame_done || last_mb_started_mclk) reading_frame_r <= 0;
else if (frame_started_mclk) reading_frame_r <= 1;
// if (!cmprs_run || frame_start_dst_r[0]) frame_start_pend_r <= 0;
if (!cmprs_run || frame_start_conf) frame_start_pend_r <= 0;
else if ((cmprs_run && vsync_late && reading_frame_r) ||
(frame_start_dst_r[5] && bonded_mode && frames_numbers_differ)) frame_start_pend_r <= 1;
// else if (frame_start_dst_r[0]) frame_start_pend_r <= 0;
// If started frame differs from tghe source one, needs to comrfess next frame after this is done, without vsync_late
// else if (frame_start_dst_r[5] ) frame_start_pend_r <= bonded_mode && frames_numbers_differ;
// if (!cmprs_en) suspend_end <= 0;
if (!cmprs_run) suspend_end <= 0;
else if (frame_done) suspend_end <= 1;
else if (frame_start_dst_r[3]) suspend_end <= 0;
......@@ -176,7 +158,6 @@ module cmprs_frame_sync#(
cmprs_standalone);
// modified - now bit 0 is disconnected from 1..5, 1 gets from memory channel controller, may be delayed
if (!cmprs_en) frame_start_dst_r[5:1] <=0;
// else frame_start_dst_r[5:1] <= frame_start_dst_r[4:0];
else frame_start_dst_r[5:1] <= {frame_start_dst_r[4:1],frame_start_conf};
if (!cmprs_en) bonded_mode <= 0;
......@@ -188,14 +169,12 @@ module cmprs_frame_sync#(
frames_numbers_differ <= !suspend_end && (frame_number_src != frame_number); // during end of frame, before frame number is incremented
/// line_numbers_sync <= (line_unfinished_src > line_unfinished);
line_numbers_sync <= (line_unfinished_src >= line_unfinished);
suspend <= bonded_mode && (!frames_in_sync || !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync));
end
// pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(cmprs_en_xclk && vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
pulse_cross_clock last_mb_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(last_mb_started), .out_pulse(last_mb_started_mclk),.busy());
......
......@@ -108,6 +108,7 @@ module cmprs_out_fifo(
// rclk -> wclk
pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
ram_var_w_var_r #(
.COMMENT("cmprs_out_fifo"),
.REGISTERS(1),
.LOG2WIDTH_WR(4),
.LOG2WIDTH_RD(6)
......
......@@ -108,6 +108,7 @@ module cmprs_out_fifo32(
// rclk -> wclk
pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
ram_var_w_var_r #(
.COMMENT("cmprs_out_fifo32"),
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(6)
......
......@@ -117,7 +117,6 @@ module cmprs_pixel_buf_iface #(
reg [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
wire [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column
reg [ 5:0] extra_start_addr_r;
// reg [ 5:0] mb_h; // macroblock height (lost MSB - OK)
reg [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start
assign buf_ra = bufa_r;
......@@ -130,7 +129,6 @@ module cmprs_pixel_buf_iface #(
assign mb_pre_end = mb_pre_end_r;
assign mb_release_buf = mb_release_buf_r;
assign buf_rd = buf_re[1:0];
// assign data_out = do_r;
assign pre_first_out = pre_first_out_r[0];
assign pre2_first_out = pre_first_out_r[1];
`ifdef DEBUG_COMPRESSOR_SCRAMBLE
......@@ -147,7 +145,6 @@ module cmprs_pixel_buf_iface #(
`endif
always @(posedge xclk) begin
// mb_h <= mb_h_m1+1; // macroblock height
mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]};
extra_start_addr_r <= extra_start_addr_w[5:0];
mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0};
......@@ -164,10 +161,6 @@ module cmprs_pixel_buf_iface #(
//mb_pre_start
if (!frame_en) pre_first_out_r <= 0;
else pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]};
// else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
// if (!frame_en) pre2_first_out <= 0;
// else pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];
if (mb_pre_start) rows_left <= mb_h_m1;
else if (last_col) rows_left <= rows_left - 1;
......@@ -177,17 +170,14 @@ module cmprs_pixel_buf_iface #(
if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+2:1] <= 0;
// if (buf_re[0]) last_col <= 0; // ????
if (!buf_re[0]) last_col <= 0;
else last_col <= (cols_left == 1);
// if (buf_re[0]) last_row <= 0;
if (!buf_re[0]) last_row <= 0;
else if (last_col) last_row <= (rows_left == 1);
first_col <= (mb_pre_start || (last_col && !last_row));
// if (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x};
else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10);
......@@ -207,7 +197,6 @@ module cmprs_pixel_buf_iface #(
else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;
// Most time critical - calculation of the buffer address
// if (mb_pre_start) bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) bufa_r[9:0] <= {mb_start_addr}; // macroblock_x};
else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
else if (last_in_tile) bufa_r[9:0] <= tile_sa;
......
This diff is collapsed.
......@@ -78,6 +78,8 @@ module compressor393 # (
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16 = 17, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
......@@ -100,6 +102,7 @@ module compressor393 # (
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
......@@ -107,6 +110,7 @@ module compressor393 # (
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_RAW = 6, // Not comressed, raw data
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
......@@ -372,6 +376,8 @@ module compressor393 # (
.CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS),
.CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES),
.CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS),
.CMPRS_CBIT_BE16 (CMPRS_CBIT_BE16),
.CMPRS_CBIT_BE16_BITS (CMPRS_CBIT_BE16_BITS),
.CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER),
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
......@@ -392,12 +398,14 @@ module compressor393 # (
.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 (CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2),
.CMPRS_CBIT_CMODE_MONO1 (CMPRS_CBIT_CMODE_MONO1),
.CMPRS_CBIT_CMODE_MONO4 (CMPRS_CBIT_CMODE_MONO4),
.CMPRS_CBIT_CMODE_RAW (CMPRS_CBIT_CMODE_RAW),
.CMPRS_CBIT_FRAMES_SINGLE (CMPRS_CBIT_FRAMES_SINGLE),
.CMPRS_COLOR18 (CMPRS_COLOR18),
.CMPRS_COLOR20 (CMPRS_COLOR20),
.CMPRS_MONO16 (CMPRS_MONO16),
.CMPRS_JP4 (CMPRS_JP4),
.CMPRS_JP4DIFF (CMPRS_JP4DIFF),
.CMPRS_RAW (CMPRS_RAW),
.CMPRS_MONO8 (CMPRS_MONO8),
.CMPRS_FRMT_MBCM1 (CMPRS_FRMT_MBCM1),
.CMPRS_FRMT_MBCM1_BITS (CMPRS_FRMT_MBCM1_BITS),
......
......@@ -53,7 +53,7 @@ module encoderDCAC393(
input first_blockz, // first block input (@zds)
input zds, // strobe - one ahead of the DC component output
output reg last, //
output reg [15:0] do,
output reg [15:0] dout,
output reg dv,
// just for debug
output comp_lastinmbo,
......@@ -132,7 +132,7 @@ module encoderDCAC393(
(cntr[5:0]==6'h3f),
ac_in[11:0]}};
was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen;
if (pre_dv) do <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
if (pre_dv) dout <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
dv <= pre_dv;
DCACen <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f))); // adjust
if (!DCACen) cntr[5:0] <=6'b0;
......
......@@ -59,7 +59,7 @@ module focus_sharp393(
input quant_ds, // quantizator ds
input [12:0] quant_d, // [11:0]quantizator data output
input [15:0] quant_dc_tdo, // [15:0], MSB aligned coefficient for the DC component (used in focus module)
output reg [12:0] do, // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
output reg [12:0] dout, // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
output reg ds, // data out strobe (one ahead of the start of dv)
output reg [31:0] hifreq); //[31:0]) // accumulated high frequency components in a frame sub-window
......@@ -248,7 +248,7 @@ module focus_sharp393(
ds <= pre_ds;
pre_do[12:0] <= next_do[12:0];
need_corr_max <=luma_dc_out && (mode[1:0]!=2'h0);
do[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?
dout[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?
{2'b0,quant_dc_tdo[15:5]} :
pre_do[12:0];
end
......
......@@ -4,7 +4,7 @@
* @date 2015-10-26
* @author Andrey Filippov
*
* @brief Wrapper fior several JPEG/JP4 compression modules. It includes
* @brief Wrapper for several JPEG/JP4 compression modules. It includes
* - Huffman encoder (huffman_snglclk),
* - bit stuffer (bit_stuffer_27_32),
* - escapes 0xff with 0x00 (bit_stuffer_escape)
......@@ -66,6 +66,7 @@ module huffman_stuffer_meta(
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
//TODO: Should be generated fro raw also
input color_first, // @fradv_clk only used for timestamp
// outputs @ negedge clk
output [31:0] data_out, // [31:0] output data
......@@ -154,7 +155,8 @@ module huffman_stuffer_meta(
.flush_out (escape_flush_out) // output reg
);
bit_stuffer_metadata bit_stuffer_metadata_i (
// TODO: Insert raw data here, always 4x bytes (actually 16*16*(1..2))
bit_stuffer_raw_metadata bit_stuffer_metadata_i (
.mclk (mclk), // input
.mrst (mrst), // input
.xclk (xclk), // input
......
/*!
* <b>Module:</b>huffman_stuffer_raw_meta
* @file huffman_stuffer_raw_meta.v
* @date 2015-10-26
* @author Andrey Filippov
*
* @brief Wrapper for several JPEG/JP4 compression modules. It includes
* - Huffman encoder (huffman_snglclk),
* - bit stuffer (bit_stuffer_27_32),
* - escapes 0xff with 0x00 (bit_stuffer_escape)
* - inserts meta-data (timestamp and data length) (bit_stuffer_metadata)
*
* This is a "new" (made for x393 project) part of the JPEG/JP4 comressor
* that eliminates use of the double frequency clock.
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* huffman_stuffer_raw_meta.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* huffman_stuffer_raw_meta.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module huffman_stuffer_raw_meta(
input mclk, // system clock to write tables
input mrst,
input xclk, // pixel clock, sync to incoming data
input en_huffman, // @xclk
input en_stuffer, // @xclk
input abort_stuffer, // @ any, valid ffor raw also
// Interface to program Huffman tables
input tser_we, // enable write to a table
input tser_a_not_d, // address/not data distributed to submodules
input [ 7:0] tser_d, // byte-wide serialized tables address/data to submodules
// Input data
input [15:0] di, // [15:0] specially RLL prepared 16-bit data (to FIFO) (sync to xclk)
input ds, // di valid strobe (sync to xclk)
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
//TODO: Should be generated for raw also
input color_first, // @fradv_clk only used for timestamp
// RAW mode ports, all @ xclk
input compressed_mode, // operating in raw mode (uncompressed)
input raw_mode, // operating in raw mode (uncompressed)
input raw_be16, // swap byte pairs to outut 16-bit big endian data
input [7:0] raw_bytes, // raw bypass byte data in little endian order
input raw_start, // single-cycle set "running"
input raw_prefb, // 1 cycle before sequence of 4 bytes
input raw_ts_copy, // single-cycle copy timestamp (some time before flush)
input raw_flush, // flush remaining data, length and timestamp
// outputs @ negedge clk
output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid
output done, // reset by !en, goes high after some delay after flushing
output running, // from registering timestamp until done
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk // 1-cycle flush output @ clk_flush
`ifdef DEBUG_RING
,output test_lbw,
output gotLastBlock, // last block done - flush the rest bits
output [3:0] dbg_etrax_dma
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
`endif
);
wire [26:0] huffman_do27;
wire [4:0] huffman_dl;
wire huffman_dv;
wire huffman_flush;
wire huffman_last_block;
wire [31:0] stuffer_do32;
wire [1:0] stuffer_bytes;
wire stuffer_dv;
wire stuffer_flush_out;
wire [31:0] escape_do32;
wire [1:0] escape_bytes;
wire escape_dv;
wire escape_flush_out;
huffman_snglclk huffman_snglclk_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.mclk (mclk), // input
.tser_we (tser_we), // input
.tser_a_not_d (tser_a_not_d), // input
.tser_d (tser_d), // input[7:0]
.di (di), // input[15:0]
.ds (ds), // input
.do27 (huffman_do27), // output[26:0]
.dl (huffman_dl), // output[4:0]
.dv (huffman_dv), // output
.flush (huffman_flush), // output
.last_block (huffman_last_block), // output
`ifdef DEBUG_RING
.test_lbw (test_lbw),
.gotLastBlock (gotLastBlock), // last block done - flush the rest bits
`else
.test_lbw (),
.gotLastBlock (), // last block done - flush the rest bits
`endif
.clk_flush (clk_flush), // input
.flush_clk (flush_clk), // output
.fifo_or_full() // output
);
bit_stuffer_27_32 #(
.DIN_LEN(27)
) bit_stuffer_27_32_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (huffman_do27), // input[26:0]
.dlen (huffman_dl), // input[4:0]
.ds (huffman_dv), // input
.flush_in (huffman_flush), // input
.d_out (stuffer_do32), // output[31:0]
.bytes_out (stuffer_bytes), // output[1:0] reg
.dv (stuffer_dv), // output reg
.flush_out (stuffer_flush_out) // output reg
);
bit_stuffer_escape bit_stuffer_escape_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (stuffer_do32), // input[31:0]
.bytes_in (stuffer_bytes), // input[1:0]
.in_stb (stuffer_dv), // input
.flush_in (stuffer_flush_out), // input
.d_out (escape_do32), // output[31:0] reg
.bytes_out (escape_bytes), // output[1:0] reg
.dv (escape_dv), // output reg
.flush_out (escape_flush_out) // output reg
);
// TODO: Insert raw data here, always 4x bytes (actually 16*16*(1..2))
bit_stuffer_raw_metadata bit_stuffer_metadata_i (
.mclk (mclk), // input
.mrst (mrst), // input
.xclk (xclk), // input
.xrst (~en_stuffer), // input
.last_block (huffman_last_block), // input TODO: leading edge is needed for raw (to xfer timestamp) - not anymore
.ts_pre_stb (ts_pre_stb), // input
.ts_data (ts_data), // input[7:0]
.color_first (color_first), // input
.din (escape_do32), // input[31:0]
.bytes_in (escape_bytes), // input[1:0]
.in_stb (escape_dv), // input
.flush (escape_flush_out), // input
.abort (abort_stuffer), // input
.compressed_mode(compressed_mode), // input
.raw_mode (raw_mode), // input
.raw_be16 (raw_be16), // input
.raw_bytes (raw_bytes), // input[7:0]
.raw_start (raw_start), // input
.raw_prefb (raw_prefb), // input
.raw_ts_copy (raw_ts_copy), // input
.raw_flush (raw_flush), // input
.data_out (data_out), // output[31:0] reg
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
`ifdef DEBUG_RING
,.dbg_etrax_dma (dbg_etrax_dma), // output[3:0] reg
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) // output[7:0]
`endif
);
endmodule
This diff is collapsed.
......@@ -58,7 +58,7 @@ module quantizer393(
input first_in, // first block in (valid @ start)
output reg first_out, // valid @ ds
input [12:0] di, // [11:0] pixel data in (signed)
output reg [12:0] do, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
output reg [12:0] dout, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
output dv, // data out valid
output ds, // data out strobe (one ahead of the start of dv)
output reg [15:0] dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)
......@@ -157,13 +157,11 @@ module quantizer393(
assign dcc_data[15:0]=sel_satnum?
{n255[7:0],n000[7:0]}:
{dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};
// assign do[12:0]=zigzag_q[12:0];
assign qmul[27:0]=tdor[15:0]*d3[11:0];
assign start_out = zwe && (zwa[5:0]== 6'h3f); //adjust?
assign copy_dc_tdo = zwe && (zwa[5:0]== 6'h37); // not critical
// assign next_dv=en && (ds || (dv && (zra[5:0]!=6'h00)));
always @ (posedge clk) begin
d1[12:0] <= di[12:0];
//inv_sign
......@@ -218,7 +216,7 @@ module quantizer393(
if (!en) ren[3:1] <= 0;
else ren[3:1] <= ren [2:0];
if (ren[2]) do[12:0] <= zigzag_q[12:0];
if (ren[2]) dout[12:0] <= zigzag_q[12:0];
if (start_a) first_interm <= first_in;
if (start_out) first_out <=first_interm;
......
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>x393</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.python.pydev.PyDevBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.elphel.vdt.veditor.HdlNature</nature>
<nature>org.python.pydev.pythonNature</nature>
</natures>
</projectDescription>
......@@ -35,7 +35,53 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300da; //parallel - sata v.13 - tolerating elidle from device during comreset/cominit -0.014 /1, 81.38%,
parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, foxed bug, all met
// parameter FPGA_VERSION = 32'h03930110; //A serial - 17.4 - restored delay after linear, foxed bug, timing met
// parameter FPGA_VERSION = 32'h03930110; // serial - 17.4 - restored delay after linear, foxed bug, timing failed
// parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, foxed bug, all met
// parameter FPGA_VERSION = 32'h03930106; // parallel - 17.4 - increased delay after linear read all met
// parameter FPGA_VERSION = 32'h03930105; // parallel - 17.4 - fixed wide raw frames all met
// parameter FPGA_VERSION = 32'h03930104; // parallel - 17.4 - added RAW mode (for tiff files) timing met
// parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
// parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix
// parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface - met
// parameter FPGA_VERSION = 32'h03930100; // serial - 17.4 - disabling SOF when setting interface timing OK
// parameter FPGA_VERSION = 32'h039300ff; // serial - 15.3 - same, suspected bitstream problems
// parameter FPGA_VERSION = 32'h039300fe; // serial - 17.4 - same, suspected bitstream problems no timing errors
// parameter FPGA_VERSION = 32'h039300fd; // serial - 17.4 - monitor lanes barrel (0..3)
// parameter FPGA_VERSION = 32'h039300fc; // serial - 17.4 - skipping first lines? pclk dsp1->dsp2 3*54ps
// parameter FPGA_VERSION = 32'h039300fb; // serial - 17.4 - serial, adding trigger control, lanes_alive (violated xclk by 0.004)
// parameter FPGA_VERSION = 32'h039300fa; // serial - 15.3 - serial, modifying lens_flat - timing met
// parameter FPGA_VERSION = 32'h039300f4; // parallel - 17.4 - , modifying lens_flat - timing met
// parameter FPGA_VERSION = 32'h039300f9; // serial - 17.4 - serial, modifying lens_flat - timing met
// parameter FPGA_VERSION = 32'h039300f8; // serial - 17.4 - failed pclk by 0.122
// parameter FPGA_VERSION = 32'h039300f3; //parallel - 17.4 - adding buffer frame number to status (no debug)
// parameter FPGA_VERSION = 32'h039300f2; //parallel - 17.4 - inactive debug, OK on fresh
// parameter FPGA_VERSION = 32'h039300f1; //parallel - 17.4 - without power optimize failed, second - OK
// parameter FPGA_VERSION = 32'h039300f0; //parallel - 17.4 - retry with spells in clean directory - failed
// parameter FPGA_VERSION = 32'h039300ef; //parallel - 17.4 - trying more set_param VivadoSynthesis-20180203230051566.log - OK!
// parameter FPGA_VERSION = 32'h039300ee; //parallel - 17.4 - save after re-running vivado, same dir - bad
// parameter FPGA_VERSION = 32'h039300ed; //parallel - 17.4 - twice synth+par, then bit - good
// parameter FPGA_VERSION = 32'h039300edc; //parallel - 17.4 - twice synth, then bit - bad
// parameter FPGA_VERSION = 32'h039300ec; //parallel - 17.4 - same, no debug, nofresh maxThreads 1- good
// parameter FPGA_VERSION = 32'h039300eb; //parallel - 17.4 - same, no debug, fresh maxThreads 1 - bad (bad numbers)
// parameter FPGA_VERSION = 32'h039300ea; //parallel - 17.4 - same, no debug, nofresh - good
// parameter FPGA_VERSION = 32'h039300e9; //parallel - 17.4 - same, no debug, nofresh - bad, seemed goog log
// parameter FPGA_VERSION = 32'h039300e8; //parallel - 17.4 - same, no debug, fresh - bad
// parameter FPGA_VERSION = 32'h039300e7; //parallel - 17.4 - same, no debug - good
// parameter FPGA_VERSION = 32'h039300e6; //parallel - 17.4 - clean, debug - OK
// parameter FPGA_VERSION = 32'h039300e5; //parallel - 17.4 - clean, debug - OK
// parameter FPGA_VERSION = 32'h039300e4; //parallel - 17.4 - same with clean remote directory - bad
// parameter FPGA_VERSION = 32'h039300e3; //parallel - 17.4 - good
// parameter FPGA_VERSION = 32'h039300e2; //parallel - 17.4 - no error, bad again
// parameter FPGA_VERSION = 32'h039300e1; //parallel - 17.4 - changing attributes to match old -bad!
// parameter FPGA_VERSION = 32'h039300e0; //parallel - 17.4 - disabled all debug - OK
// parameter FPGA_VERSION = 32'h039300df; //parallel - 17.4 - all debug ==0 - met, OK
// parameter FPGA_VERSION = 32'h039300de; //parallel - 17.4 - changing clock,met, good (clock - hclk)
// parameter FPGA_VERSION = 32'h039300dd; //parallel - 17.4 - adding debug to SAXI1GP - OK
// parameter FPGA_VERSION = 32'h039300dc; //parallel - 15.3 - adding debug to SAXI1GP - -0.114
// parameter FPGA_VERSION = 32'h039300db; //parallel - trying to migrate to 17.04
// parameter FPGA_VERSION = 32'h039300da; //parallel - sata v.13 - tolerating elidle from device during comreset/cominit -0.014 /1, 81.38%,
// parameter FPGA_VERSION = 32'h039300d9; //parallel - correcting histograms -0.022/1, 79.60%
// parameter FPGA_VERSION = 32'h039300d8; //parallel - SATA is now logging irq on/off -0.054 /16, 80.50%
// parameter FPGA_VERSION = 32'h039300d7; //parallel - updated SATA (v12) all met, 80.32%
......
......@@ -51,4 +51,3 @@ localparam DLY_LANE1_IDELAY = 72'h186c6c726c746a7173;
localparam DLY_CMDA = 256'hd3d3dad2d1cccad2505050505050505050d4d1d1d2d2dbcad2cad3d4d2cacbd1;
localparam DLY_PHASE = 8'h34;
// localparam DFLT_WBUF_DELAY = 4'h9;
\ No newline at end of file
......@@ -292,6 +292,7 @@
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_LINEAR = 7, // Use linear mode instead of tiled
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
......@@ -356,6 +357,16 @@
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h20, 'h22, 'h24, 'h26
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h21, 'h23, 'h25, 'h27
// parameters to measure sensor timing from (last){sof,eof,sol, eol} to next{sof,eof,sol, eol}
parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43
parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor
parameter SENSOR_TIMING_BITS = 24, // increment to the next sensor
parameter SENSOR_TIMING_START = 16, // bit # in JTAB control word to start timing measurement (now f = 660/4 = 165)
parameter SENSOR_TIMING_LANE = 14, // 15:14 - select lane
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - eof, 2 - sol, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - eof, 2 - sol, 3 eol
parameter SENSOR_NUM_HISTOGRAM= 1, //was 3 trying just one histogram (see utilization) 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "BUF32", // "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_NUM_SUBCHN = 3, // number of subchannels for his sensor ports (1..4)
......@@ -478,8 +489,8 @@
//`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
//`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
......@@ -702,6 +713,8 @@
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16 = 17, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
......@@ -724,6 +737,7 @@
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
......@@ -732,6 +746,7 @@
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_RAW = 6, // Not comressed, raw data
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
......
......@@ -79,17 +79,43 @@
// parameter SENSOR_IMAGE_TYPE2 = "NORM11", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "NORM12",
parameter SENSOR_IMAGE_TYPE0 = "NORM13",
parameter SENSOR_IMAGE_TYPE1 = "NORM13",
parameter SENSOR_IMAGE_TYPE2 = "NORM14", // 4",
parameter SENSOR_IMAGE_TYPE3 = "NORM15",
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4,
// parameter SENSOR_IMAGE_TYPE0 = "TEST01-1044X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "TEST01-1044X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "TEST01-1044X36", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "TEST01-1044X36", // "NORM15",