...
 
Commits (2)
......@@ -2004,7 +2004,21 @@ simul_axi_hp_wr #(
.uart_in (sns1_dp[4]), // input sns_txd
.uart_out (sns1_dn[4]) // output sns_rxd
);
`ifdef BOSON_REVA // 103993 REVA board
simul_103993A_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_1_i (
.ta({2'b10, boson_pxd1[ 4: 0]}), // input[6:0]
.tb({2'b10, boson_pxd1[ 9: 5]}), // input[6:0]
.tc({2'b10, boson_pxd1[14:10]}), // input[6:0]
.td({3'b100,boson_dvalid1, boson_vsync1,boson_hsync1,boson_pxd1[15]}), // input[6:0]
.pclk(boson_pclk1), // input
.dp(sns1_dp[3:0]), // output[3:0]
.dn(sns1_dn[3:0]), // output[3:0]
.clkp(sns1_clkp), // output
.clkn(sns1_clkn) // output
);
`else
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_1_i (
......@@ -2020,7 +2034,7 @@ simul_axi_hp_wr #(
.clkp (sns1_clkp), // output
.clkn (sns1_clkn) // output
);
`endif
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
......@@ -2044,7 +2058,21 @@ simul_axi_hp_wr #(
.uart_in (sns2_dp[4]), // input sns_txd
.uart_out (sns2_dn[4]) // output sns_rxd
);
`ifdef BOSON_REVA // 103993 REVA board
simul_103993A_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_2_i (
.ta({2'b10, boson_pxd2[ 4: 0]}), // input[6:0]
.tb({2'b10, boson_pxd2[ 9: 5]}), // input[6:0]
.tc({2'b10, boson_pxd2[14:10]}), // input[6:0]
.td({3'b100,boson_dvalid2, boson_vsync2,boson_hsync2,boson_pxd2[15]}), // input[6:0]
.pclk(boson_pclk2), // input
.dp(sns2_dp[3:0]), // output[3:0]
.dn(sns2_dn[3:0]), // output[3:0]
.clkp(sns2_clkp), // output
.clkn(sns2_clkn) // output
);
`else
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_2_i (
......@@ -2060,6 +2088,7 @@ simul_axi_hp_wr #(
.clkp (sns2_clkp), // output
.clkn (sns2_clkn) // output
);
`endif
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
......@@ -2085,6 +2114,21 @@ simul_axi_hp_wr #(
.uart_out (sns3_dn[4]) // output sns_rxd
);
`ifdef BOSON_REVA // 103993 REVA board
simul_103993A_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_3_i (
.ta({2'b10, boson_pxd3[ 4: 0]}), // input[6:0]
.tb({2'b10, boson_pxd3[ 9: 5]}), // input[6:0]
.tc({2'b10, boson_pxd3[14:10]}), // input[6:0]
.td({3'b100,boson_dvalid3, boson_vsync3,boson_hsync3,boson_pxd3[15]}), // input[6:0]
.pclk(boson_pclk3), // input
.dp(sns3_dp[3:0]), // output[3:0]
.dn(sns3_dn[3:0]), // output[3:0]
.clkp(sns3_clkp), // output
.clkn(sns3_clkn) // output
);
`else
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_3_i (
......@@ -2100,6 +2144,7 @@ simul_axi_hp_wr #(
.clkp (sns3_clkp), // output
.clkn (sns3_clkn) // output
);
`endif
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
......@@ -2124,7 +2169,21 @@ simul_axi_hp_wr #(
.uart_in (sns4_dp[4]), // input sns_txd
.uart_out (sns4_dn[4]) // output sns_rxd
);
`ifdef BOSON_REVA // 103993 REVA board
simul_103993A_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_4_i (
.ta({2'b10, boson_pxd4[ 4: 0]}), // input[6:0]
.tb({2'b10, boson_pxd4[ 9: 5]}), // input[6:0]
.tc({2'b10, boson_pxd4[14:10]}), // input[6:0]
.td({3'b100,boson_dvalid4, boson_vsync4,boson_hsync4,boson_pxd4[15]}), // input[6:0]
.pclk(boson_pclk4), // input
.dp(sns4_dp[3:0]), // output[3:0]
.dn(sns4_dn[3:0]), // output[3:0]
.clkp(sns4_clkp), // output
.clkn(sns4_clkn) // output
);
`else
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_4_i (
......@@ -2140,9 +2199,7 @@ simul_axi_hp_wr #(
.clkp (sns4_clkp), // output
.clkn (sns4_clkn) // output
);
`endif
`else
......
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03934006; // Boson640, adjusted initial phase to 70.5 degrees (47 counts)
parameter FPGA_VERSION = 32'h03934010; // Boson640, for 103993A
// parameter FPGA_VERSION = 32'h03934006; // Boson640, adjusted initial phase to 70.5 degrees (47 counts)
// parameter FPGA_VERSION = 32'h03934005; // Boson640, testing
// parameter FPGA_VERSION = 32'h03934005; // Boson640, implementing DRP to control MMCME2/PLLE2 trying more BUFR
// parameter FPGA_VERSION = 32'h03934004; // Boson640, implementing DRP to control MMCME2/PLLE2
......
......@@ -727,12 +727,17 @@
`endif
`elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
`ifdef BOSON_REVA
parameter CLKFBOUT_MULT_SENSOR = 35, // 945 MHz 28, // 27 MHz --> 756 MHz
`else
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
`endif
//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
`ifdef SIMULATION
parameter CLKFBOUT_PHASE_SENSOR = 54.0, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`else
parameter CLKFBOUT_PHASE_SENSOR = 70.5, // -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
//It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 35.000] = 1.286
parameter CLKFBOUT_PHASE_SENSOR = 0.0, // 70.5, // -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`endif
parameter PCLK_PHASE = 0.000, // not used
parameter IPCLK1X_PHASE = 0.000, // -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
......@@ -850,7 +855,11 @@
//`ifdef HISPI
parameter HISPI_MSB_FIRST = 0,
`ifdef BOSON
parameter HISPI_NUMLANES = 3,
`ifdef BOSON_REVA
parameter HISPI_NUMLANES = 4,
`else
parameter HISPI_NUMLANES = 3,
`endif
`else
parameter HISPI_NUMLANES = 4,
`endif
......
......@@ -1951,7 +1951,8 @@ uart_print_packet 0 False False
ClkReg1, ClkReg2 = self.drp_phase_addr(clk_out)
data1 = self.drp_read_reg(num_sensor, ClkReg1)
data2 = self.drp_read_reg(num_sensor, ClkReg2)
phase = ((data1 >> 13) & 7) | ((data2 & 0x1f) << 3)
# phase = ((data1 >> 13) & 7) | ((data2 & 0x1f) << 3)
phase = ((data1 >> 13) & 7) | ((data2 & 0x3f) << 3)
return phase
def drp_write_clock_phase(self,
......@@ -1967,9 +1968,9 @@ uart_print_packet 0 False False
ClkReg1, ClkReg2 = self.drp_phase_addr(clk_out)
data1 = (phase & 7) << 13
data2 = (phase >> 3) & 0x1f
data2 = (phase >> 3) & 0x3f
self.drp_write_reg(num_sensor, addr=ClkReg1, data=data1, mask=0xe000)
self.drp_write_reg(num_sensor, addr=ClkReg2, data=data2, mask=0x001f)
self.drp_write_reg(num_sensor, addr=ClkReg2, data=data2, mask=0x003f)
def jtag_get_tdo(self, chn):
seq_num = ((self.get_status_sensor_io(num_sensor = chn) >> 26) + 1) & 0x3f
......
......@@ -118,7 +118,11 @@ module sens_103993 #(
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
// parameter LVDS_MSB_FIRST = 0,
`ifdef BOSON_REVA
parameter NUMLANES = 4,
`else
parameter NUMLANES = 3,
`endif
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
parameter LVDS_CAPACITANCE = "DONT_CARE",
......@@ -283,7 +287,11 @@ module sens_103993 #(
wire senspgmin; // detect sensorboard
// GP0..GP3 are not yet used, fake-use gp_comb to keep
wire [3:0] gp;
`ifdef BOSON_REVA
wire [0:0] dummy; // to keep iostandard of unused pins in a bank
`else
wire [2:0] dummy; // to keep iostandard of unused pins in a bank
`endif
wire gp_comb = (^gp[3:0]) ^ (^dummy);
reg test_patt;
reg [7:0] perr_cntr;
......@@ -483,13 +491,76 @@ module sens_103993 #(
wire clkin_pxd_stopped_mmcm1;
wire clkfb_pxd_stopped_mmcm1;
*/
`ifdef USE_SERIALIZER_103993
`ifdef BOSON_REVA
sens_103993A_lanes #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), // 37.037),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), // (30),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), // (54.0),
.PCLK_PHASE (PCLK_PHASE), // (0.000),
.IPCLK1X_PHASE (IPCLK1X_PHASE), //(0.000), // not actually used
.IPCLK2X_PHASE (IPCLK2X_PHASE), //(0.000),
.BUF_PCLK (BUF_PCLK), // "BUFR"),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X), // "BUFR"),
.BUF_CLK_FB (BUF_CLK_FB),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), // 1),
.SENS_REF_JITTER1 (SENS_REF_JITTER1), // 0.010),
.SENS_REF_JITTER2 (SENS_REF_JITTER2), // 0.010),
.SENS_SS_EN (SENS_SS_EN), // "FALSE"),
.SENS_SS_MODE (SENS_SS_MODE), // "CENTER_HIGH"),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), // 10000),
.NUMLANES (NUMLANES), // 3),
.LVDS_DELAY_CLK (LVDS_DELAY_CLK), // "FALSE"),
.LVDS_MMCM (LVDS_MMCM), // "TRUE"),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE), // "DONT_CARE"),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM), // "TRUE"),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT), // "FALSE"),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS), // "TRUE"),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE), // "0"),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR), // "TRUE"),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE), // "AUTO"),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD), // "DIFF_SSTL18_I")
.DEGLITCH_DVALID (1),
.DEGLITCH_HSYNC (3),
.DEGLITCH_VSYNC (7)
) sens_103993_l3_i ( // same instance name
.pclk (pclk), // output
.prsts (prsts), // input,
.sns_dp (sns_dp[3:0]), // input[3:0]
.sns_dn (sns_dn[3:0]), // input[3:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.pxd_out (pxd_w), // output[15:0]
.vsync (vsync), // output
.hsync (hsync), // output
.dvalid (dvalid_w), // output
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r[31:0]), // input[31:0]
.set_idelay ({NUMLANES{set_idelays}}),// input[2:0]
.apply_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
.rst_mmcm (rst_mmcm), // input
.perr (perr), // output
.test_out (test_out), // output[7:0] // should be 0x17
.locked_pxd_mmcm (locked_pclk), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm), // output
.drp_cmd (drp_cmd), // input[1:0]
.drp_bit (drp_bit), // output
.drp_odd_bit (drp_odd_bit) // output
);
`elsif USE_SERIALIZER_103993
sens_103993_lanes #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
// .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), // 37.037),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), // (30),
......@@ -767,7 +838,8 @@ module sens_103993 #(
.T (1'b0) // input
);
*/
`ifdef BOSON_REVA
`else
ibuf_ibufg #(
.CAPACITANCE (PXD_CAPACITANCE),
.IBUF_DELAY_VALUE("0"),
......@@ -788,7 +860,7 @@ module sens_103993 #(
.O(dummy[2]), // output
.I(sns_dp[3]) // input
);
`endif
// end of dummy
// pulldown to detect sensor presense
......
This diff is collapsed.
/*!
* <b>Module:</b> sens_103993A_lane
* @file sens_103993A_lane.v
* @date 2021-03-26
* @author eyesis
*
* @brief
*
* @copyright Copyright (c) 2021 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_103993A_lane.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993A_lane.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993A_lane#(
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
// parameter NUMLANES = 3,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)(
input mclk,
input mrst,
input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input ld_idelay, // mclk synchronous load idelay value
input apply_idelay, // mclk synchronous set idealy value
input pclk, // 27 MHz
input ipclk2x, // 135 MHz
input ipclk1x, // 67.5 MHz
input rst, // reset// @posedge iclk
input for_pclk, // @posedge ipclk1x copy 10 bits form ipclk1x domain to pclk (alternating 2/3 iplck1x intervals)
input for_pclk_last, // @posedge ipclk1x: next for_pclk will apply to last 7 bits (count 0..3)
input din_p,
input din_n,
output [6:0] dout);
wire din;
wire din_dly;
wire [9:0] deser_w; // deserializer 4-bit output and previous values
reg [5:0] deser_r;
reg [6:0] dout_r;
reg [6:0] pre_dout_r;
reg [3:0] bshift; // one-hot shift of the data output
assign dout=dout_r;
assign deser_w[9:4] = deser_r[5:0];
generate
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "40") begin
ibufds_ibufgds_40 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "50") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // inputpre_dout_r
);
end else if (LVDS_UNTUNED_SPLIT == "60") begin
ibufds_ibufgds_60 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end
endgenerate
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) pxd_dly_i(
.clk (mclk),
.rst (mrst),
.set (apply_idelay),
.ld (ld_idelay),
.delay (dly_data[7:3]),
.data_in (din),
.data_out (din_dly)
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN ("FALSE"),
.MSB_FIRST (1) // MSB is received first
) iserdes_pxd_i (
.iclk (ipclk2x), // source-synchronous clock
.oclk (ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div (ipclk1x), // oclk divided by 2, front aligned
.inv_clk_div (1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst (rst), // reset
.d_direct (1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly (din_dly), // serial input from idelay
.dout (deser_w[3:0]), // parallel data out
.comb_out() // output
);
always @ (negedge ipclk1x) begin
deser_r <= {deser_r[1:0],deser_w[3:0]};
end
always @ (negedge ipclk1x) begin
if (for_pclk) bshift <= for_pclk_last ? 4'b0001 : {bshift[2:0],1'b0};
if (for_pclk) pre_dout_r <=
({7{bshift[0]}} & deser_w[6:0]) |
({7{bshift[1]}} & deser_w[7:1]) |
({7{bshift[2]}} & deser_w[8:2]) |
({7{bshift[3]}} & deser_w[9:3]);
end
always @ (posedge pclk) begin
dout_r <= pre_dout_r;
end
endmodule
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/*!
* <b>Module:</b> simul_103993A_serializer
* @file simul_103993A_serializer.v
* @date 2020-12-23
* @author eyesis
*
* @brief Serializer for Boson640 output based on SN65LVDS301
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* simul_103993A_serializer.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_103993A_serializer.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_103993A_serializer#(
parameter PCLK_FREQ_MHZ = 27.0
)(
input [6:0] ta,
input [6:0] tb,
input [6:0] tc,
input [6:0] td,
input pclk,
output [3:0] dp,
output [3:0] dn,
output clkp,
output clkn
);
localparam PERIOD = 1000.0/PCLK_FREQ_MHZ;
wire [13:0] dclocks;
assign #(PERIOD/14) dclocks[ 0] = pclk;
assign #(PERIOD/14) dclocks[ 1] = dclocks[ 0];
assign #(PERIOD/14) dclocks[ 2] = dclocks[ 1];
assign #(PERIOD/14) dclocks[ 3] = dclocks[ 2];
assign #(PERIOD/14) dclocks[ 4] = dclocks[ 3];
assign #(PERIOD/14) dclocks[ 5] = dclocks[ 4];
assign #(PERIOD/14) dclocks[ 6] = dclocks[ 5];
assign #(PERIOD/14) dclocks[ 6] = dclocks[ 5];
assign #(PERIOD/14) dclocks[ 7] = dclocks[ 6];
assign #(PERIOD/14) dclocks[ 8] = dclocks[ 7];
assign #(PERIOD/14) dclocks[ 9] = dclocks[ 8];
assign #(PERIOD/14) dclocks[10] = dclocks[ 9];
assign #(PERIOD/14) dclocks[11] = dclocks[10];
assign #(PERIOD/14) dclocks[12] = dclocks[11];
assign #(PERIOD/14) dclocks[13] = dclocks[12];
wire clk7 = (~dclocks[ 1] & dclocks[ 0]) |
(~dclocks[ 3] & dclocks[ 2]) |
(~dclocks[ 5] & dclocks[ 4]) |
(~dclocks[ 7] & dclocks[ 6]) |
(~dclocks[ 9] & dclocks[ 8]) |
(~dclocks[11] & dclocks[10]) |
(~dclocks[13] & dclocks[12]);
reg [6:0] r_ta;
reg [6:0] r_tb;
reg [6:0] r_tc;
reg [6:0] r_td;
reg [6:0] sr_ta;
reg [6:0] sr_tb;
reg [6:0] sr_tc;
reg [6:0] sr_td;
reg [6:0] sr_clk;
reg [1:0] clk_r;
reg set_sr;
assign dp = {sr_td[6], sr_tc[6], sr_tb[6], sr_ta[6]};
assign dn = ~{sr_td[6], sr_tc[6], sr_tb[6], sr_ta[6]};
assign clkp = sr_clk [6];
assign clkn = ~sr_clk [6];
always @ (posedge pclk) begin
r_ta <= ta;
r_tb <= tb;
r_tc <= tc;
r_td <= td;
end
always @ (posedge clk7) begin
clk_r <= {clk_r[0], pclk};
set_sr <= clk_r[0] && !clk_r[1];
if (set_sr) begin
sr_ta <= r_ta;
sr_tb <= r_tb;
sr_tc <= r_tc;
sr_td <= r_td;
sr_clk <= 7'b1100011;
end else begin
sr_ta <= {sr_ta[5:0], 1'b0};
sr_tb <= {sr_tb[5:0], 1'b0};
sr_tc <= {sr_tc[5:0], 1'b0};
sr_td <= {sr_td[5:0], 1'b0};
sr_clk <= {sr_clk[5:0], 1'b0};
end
end
endmodule
......@@ -81,6 +81,7 @@
`ifdef BOSON
`define PCLK_MASTER /* pclk is generated by the sensors, no global pclk and prst!*/
`define BOSON_REVA 1 /* 103993 REVA board*/
`endif
`define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393
......
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