...
 
Commits (2)
......@@ -66,5 +66,5 @@ html.tar.gz
/sysroots
/image
/scripts
py393-p2
*.~*
......@@ -1982,7 +1982,7 @@ simul_axi_hp_wr #(
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_1_i (
.mrst (sns1_dp[7]), // input
.single (boson_single), // input
.single (1'b0), // boson_single), // input
.ext_sync (sns1_ctl), // input
.pxd (boson_pxd1), // output[15:0]
.pclk (boson_pclk1), // output
......@@ -2021,7 +2021,7 @@ simul_axi_hp_wr #(
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_2_i (
.mrst (sns2_dp[7]), // input
.single (boson_single), // input
.single (1'b0), // boson_single), // input
.ext_sync (sns2_ctl), // input
.pxd (boson_pxd2), // output[15:0]
.pclk (boson_pclk2), // output
......
......@@ -667,6 +667,24 @@
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// for BOSON:
parameter UART_START_FRAME_BYTE = 'h8E,
parameter UART_END_FRAME_BYTE = 'hAE,
parameter UART_ESCAPE_BYTE = 'h9E,
parameter UART_REPLACED_START_FRAME_BYTE = 'h81,
parameter UART_REPLACED_END_FRAME_BYTE = 'hA1,
parameter UART_REPLACED_ESCAPE_BYTE = 'h91,
parameter UART_INITIAL_CRC16 = 16'h1d0f,
`ifdef SIMULATION
parameter UART_CLK_DIV = 22,
parameter UART_RX_DEBOUNCE = 6,
`else
parameter UART_CLK_DIV = 217,
parameter UART_RX_DEBOUNCE = 60,
`endif
parameter UART_EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
// endof for BOSON:
// parameters for the sensor-synchronous clock PLL
// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)
`define TWEAKING_IOSTANDARD
......
No preview for this file type
......@@ -2503,6 +2503,36 @@ T_REFI__TYPE = str
T_RFC = int
T_RFC__RAW = str
T_RFC__TYPE = str
UART_CLK_DIV = int
UART_CLK_DIV__RAW = str
UART_CLK_DIV__TYPE = str
UART_END_FRAME_BYTE = int
UART_END_FRAME_BYTE__RAW = str
UART_END_FRAME_BYTE__TYPE = str
UART_ESCAPE_BYTE = int
UART_ESCAPE_BYTE__RAW = str
UART_ESCAPE_BYTE__TYPE = str
UART_EXTIF_MODE = int
UART_EXTIF_MODE__RAW = str
UART_EXTIF_MODE__TYPE = str
UART_INITIAL_CRC16 = int
UART_INITIAL_CRC16__RAW = str
UART_INITIAL_CRC16__TYPE = str
UART_REPLACED_END_FRAME_BYTE = int
UART_REPLACED_END_FRAME_BYTE__RAW = str
UART_REPLACED_END_FRAME_BYTE__TYPE = str
UART_REPLACED_ESCAPE_BYTE = int
UART_REPLACED_ESCAPE_BYTE__RAW = str
UART_REPLACED_ESCAPE_BYTE__TYPE = str
UART_REPLACED_START_FRAME_BYTE = int
UART_REPLACED_START_FRAME_BYTE__RAW = str
UART_REPLACED_START_FRAME_BYTE__TYPE = str
UART_RX_DEBOUNCE = int
UART_RX_DEBOUNCE__RAW = str
UART_RX_DEBOUNCE__TYPE = str
UART_START_FRAME_BYTE = int
UART_START_FRAME_BYTE__RAW = str
UART_START_FRAME_BYTE__TYPE = str
VERBOSE = int
VERBOSE__RAW = str
VERBOSE__TYPE = str
......
......@@ -805,7 +805,8 @@ class X393SensCmprs(object):
mmcm_rst = True, #reset mmcm
set_delays = False)
self.x393Sensor.func_sensor_uart_ctl_boson (
self.x393Sensor.set_sensor_uart_ctl_boson (
num_sensor = num_sensor,
uart_extif_en = False,
uart_xmit_rst = True,
uart_recv_rst = True,
......@@ -822,7 +823,8 @@ class X393SensCmprs(object):
mrst = False,
mmcm_rst = False,
set_delays = False)
self.x393Sensor.func_sensor_uart_ctl_boson (
self.x393Sensor.set_sensor_uart_ctl_boson (
num_sensor = num_sensor,
uart_extif_en = True,
uart_xmit_rst = False,
uart_recv_rst = False,
......@@ -1882,7 +1884,19 @@ class X393SensCmprs(object):
bit_delay = i2c_delay,
verbose = verbose)
elif sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
pass
for module in x393_sensor.BOSON_MAP:
mod_index, indx = x393_sensor.BOSON_MAP[module]
for byte_var in range(4):
num_payload_bytes = (0,1,2,4)[byte_var]
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = indx*4,
slave_addr = num_payload_bytes,
rah = mod_index,
num_bytes = 4,
bit_delay = i2c_delay, # not used here
extif = x393_sensor.BOSON_EXTIF,
verbose = verbose)
else:
raise ("Unknown sensor type: %s"%(sensorType))
......
......@@ -50,6 +50,19 @@ SENSOR_INTERFACE_PARALLEL = "PAR12"
SENSOR_INTERFACE_HISPI = "HISPI"
SENSOR_INTERFACE_VOSPI = "VOSPI"
SENSOR_INTERFACE_BOSON = "BOSON"
BOSON_MAP = {"gao": (0x00, 0), # (module, table index - will be multiplied by 4 for 0,1,2 and 4-byte xmit command)
"roic": (0x02, 1),
"bpr": (0x03, 2),
"telemetry":(0x04, 3),
"boson": (0x05, 4),
"dvo": (0x06, 5),
"scnr": (0x08, 6),
"tnr": (0x0a, 7),
"snr": (0x0c, 8),
"sysctrl": (0x0e, 9),
"testramp": (0x10,10),
"spnr": (0x28,11)}
BOSON_EXTIF = 1 #EXTIF code for i2c commands - 0 - i2c, 1 - uart, 2,3 - reserved
class X393Sensor(object):
DRY_MODE= True # True
......@@ -57,6 +70,7 @@ class X393Sensor(object):
x393_mem=None
x393_axi_tasks=None #x393X393AxiControlStatus
x393_utils=None
uart_seq_number = 0
verbose=1
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
......@@ -632,12 +646,12 @@ class X393Sensor(object):
"""
rslt = 0
if not uart_extif_en is None:
rslt |= (3,2)[uart_extif_en] << vrlg.SENS_UART_EXTIF_EN
rslt |= (2,3)[uart_extif_en] << vrlg.SENS_UART_EXTIF_EN
if not uart_xmit_rst is None:
rslt |= (3,2)[uart_xmit_rst] << vrlg.SENS_UART_XMIT_RST
rslt |= (2,3)[uart_xmit_rst] << vrlg.SENS_UART_XMIT_RST
if not uart_recv_rst is None:
rslt |= (3,2)[uart_recv_rst] << vrlg.SENS_UART_RECV_RST
rslt |= (2,3)[uart_recv_rst] << vrlg.SENS_UART_RECV_RST
rslt |= (0,1)[uart_xmit_start] << vrlg.SENS_UART_XMIT_START
rslt |= (0,1)[uart_recv_next] << vrlg.SENS_UART_RECV_NEXT
return rslt
......@@ -874,6 +888,35 @@ class X393Sensor(object):
if verbose > 1:
print ("ta= 0x%x, td = 0x%x"%(ta,td))
def write_boson_cmd(self,
num_sensor,
rel_addr,
addr,
mod_name, # module name
func_lsb, # LSB of the function
num_payload_bytes, #0,1,2,4
data):
"""
Write i2c command to the i2c command sequencer
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
@param rel_addr - True - relative frame address, False - absolute frame address
@param addr - frame address (0..15)
@param mod_name - gao, roic, bpr, telemetry, boson, dvo, scnr, tnr, snr, sysctrl, testramp, spnr
@param func_lsb - function code LSB:
@param num_payload_bytes - number of payload bytes: 0,1,2 or 4 only
@param payload data (16 LSB used)
"""
payload_mode = (0,1,2,-1,3)[num_payload_bytes]
if payload_mode < 0:
raise ValueError('Payload of 3 bytes is not implemented, only 0,1,2 or 4 bytes are valid.')
_,mod_index = BOSON_MAP[mod_name]
wdata = ((mod_index * 4 + payload_mode) << 24) + (func_lsb & 0xff) << 16 + (data & 0xffff)
self.write_sensor_i2c (num_sensor = num_sensor,
rel_addr = rel_addr,
addr = addr,
data = wdata)
def write_sensor_reg16(self,
num_sensor,
reg_addr16,
......@@ -1496,6 +1539,110 @@ class X393Sensor(object):
# seq_num = seq_num) # input [5:0] seq_num;
# return seq_num
def uart_send_packet(self,
num_sensor,
command,
data, #bytearray
wait_ready=True,
reset_recv=True,
reset_xmit=True):
"""
Send packet to UART
@param num_sensor - sensor port number (0..3)
@param command - Full command code (module+function)
@param data - Byte array to transmit
@param wait_ready Wait until all data is sent to UART
@param reset_recv Reset UART receive channel simultaneously with transmit one
@param reset_xmit Reset UART transmit channel before sending bytes
Note: sequencer commands are disabled (may be (re)-enabled after reading response
"""
if self.uart_seq_number < 0x100:
self.uart_seq_number= 0xabcde100 + (self.uart_seq_number & 0xffffffff)
packet = bytearray()
packet.append(0) # channel number == 0
for b in (self.uart_seq_number).to_bytes(4,byteorder='big'):
packet.append(b)
for b in (command).to_bytes(4,byteorder='big'): #command
packet.append(b)
for b in (0xffffffff).to_bytes(4,byteorder='big'): # status
packet.append(b)
for b in data: # data
packet.append(b)
#reset XMIT channe, disable sequencer
#write data to FIFO, no need to wait
if reset_xmit:
self.set_sensor_uart_ctl_boson (
num_sensor = num_sensor,
uart_extif_en = False,
uart_xmit_rst = True,
uart_recv_rst = reset_recv)
self.set_sensor_uart_ctl_boson (
num_sensor = num_sensor,
uart_xmit_rst = False,
uart_recv_rst = False)
print(packet)
for b in packet:
self.set_sensor_uart_fifo_byte_boson (
num_sensor=num_sensor,
uart_tx_byte = b)
self.set_sensor_uart_ctl_boson ( # start command
num_sensor = num_sensor,
uart_xmit_start = True)
self.uart_seq_number= (self.uart_seq_number + 1) & 0xffffffff
if wait_ready:
while ((self.get_new_status(num_sensor=num_sensor) >> 25) & 1 )!= 0:
pass
def get_new_status(self,num_sensor): # same as jtag_get_tdo(self, chn):
seq_num = ((self.get_status_sensor_io(num_sensor = num_sensor) >> 26) + 1) & 0x3f
self.program_status_sensor_io(num_sensor = num_sensor,
mode = 1, # input [1:0] mode;
seq_num = seq_num) # input [5:0] seq_num;
stat = None
for _ in range(10):
stat = self.get_status_sensor_io(num_sensor = num_sensor)
if seq_num == ((stat >> 26) & 0x3f):
break
else:
print ("wait_sensio_status(): Failed to get seq_num== 0x%x, current is 0x%x"%(seq_num, (stat >> 26) & 0x3f))
return stat
def uart_receive_packet(self,
num_sensor,
enable_sequencer=True):
"""
Send packet to UART
@param num_sensor - sensor port number (0..3)
@param enable_sequencer (Re)enable sequencer commands
"""
ready = False
while not ready: # wait full packet is in FIFO
sensor_status = self.get_new_status(num_sensor=num_sensor)
recv_dav = ((sensor_status >> 15) & 1) != 0
recv_prgrs = ((sensor_status >> 14) & 1) != 0
ready = recv_dav and (not recv_prgrs)
#read byte array. TODO: improve waiting for tghe next byte?
packet = bytearray()
recv_dav = True
while recv_dav:
sensor_status = self.get_new_status(num_sensor=num_sensor)
recv_dav = ((sensor_status >> 15) & 1) != 0
recv_data = (sensor_status >> 16) & 0xff
if recv_dav:
packet.append(recv_data)
self.set_sensor_uart_ctl_boson ( # next byte
num_sensor = num_sensor,
uart_recv_next = True)
#
return packet
def jtag_get_tdo(self, chn):
seq_num = ((self.get_status_sensor_io(num_sensor = chn) >> 26) + 1) & 0x3f
self.program_status_sensor_io(num_sensor = chn,
......
......@@ -55,6 +55,9 @@ module boson_uart #(
output [7:0] rx_byte, // received byte
output rx_stb // received data strobe (valid 1 cycle before and later for 1 bit)
);
wire[7:0]debug_UART_CLK_DIV = CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = RX_DEBOUNCE; // 6,
localparam CLK_DIV_BITS = clogb2(CLK_DIV); // + 1);
localparam RX_DEBOUNCE_BITS = clogb2(RX_DEBOUNCE + 1);
reg [CLK_DIV_BITS-1:0] clk_div_cntr_rx;
......@@ -94,12 +97,14 @@ module boson_uart #(
assign stop_bit_tx = (tx_bcntr == 9);
assign rx_errw = rxd_r ? start_bit_rx : stop_bit_rx; // 1 at start, 0 at stop
assign tx_startw = tx_bit[0] && stop_bit_tx && tx_rq;
assign tx_continuew = tx_bit[0] && !stop_bit_tx;
/// assign tx_continuew = tx_bit[0] && !stop_bit_tx ;
assign tx_continuew = tx_bit[0] && !stop_bit_tx && tx_busy_r;
assign rx_byte = rx_sr[8:1];
assign rx_stb = rx_stb_r[1];
assign tx_rdy = tx_rq;
assign tx_busy = tx_busy_r || !tx_rq;
// assign tx_rdy = tx_rq;
assign tx_rdy = !tx_rq;
assign tx_busy = tx_busy_r || tx_rq; // !tx_rq;
assign txd = tx_sr[0];
always @(posedge mclk) begin
......@@ -137,20 +142,22 @@ module boson_uart #(
else if (tx_bit[1]) clk_div_cntr_tx <= CLK_DIV - 3;
else clk_div_cntr_tx <= clk_div_cntr_tx - 1;
if (mrst) tx_sr <= 10'h3ff;
else if (tx_start) tx_sr <= {1'b1, tx_r, 1'b0};
else if (tx_bit[1]) tx_sr <= {1'b1, tx_sr[9:1]};
// if (mrst) tx_sr <= 10'h3ff;
if (mrst || !tx_busy) tx_sr <= 10'h3ff;
else if (tx_start) tx_sr <= {1'b1, tx_r, 1'b0};
else if (tx_bit[1]) tx_sr <= {1'b1, tx_sr[9:1]};
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_bit[1] && stop_bit_tx) tx_busy_r <= 0;
if (mrst) tx_rq <= 0;
else if (mrst_d) tx_rq <= 1; // single-cycle turn-on after mrst
else if (tx_stb) tx_rq <= 0;
else if (tx_start) tx_rq <= 1;
/// else if (mrst_d) tx_rq <= 1; // single-cycle turn-on after mrst
else if (tx_stb) tx_rq <= 1; // 0;
else if (tx_start) tx_rq <= 0; // 1;
if (mrst) tx_bcntr <= 0;
// if (mrst) tx_bcntr <= 0;
if (mrst || !tx_busy) tx_bcntr <= 9; // stop bit ?
else if (tx_start) tx_bcntr <= 0;
else if (tx_continue) tx_bcntr <= tx_bcntr + 1;
......
......@@ -70,7 +70,7 @@ module crc16_xmodem#(
reg tx_busy_r;
reg tx_stb_crc_m;
reg tx_stb_crc_l;
reg tx_stb_crc_l2; // next cycle after tx_stb_crc_l, same as last tx_out_stb
// reg tx_stb_crc_l2; // next cycle after tx_stb_crc_l, same as last tx_out_stb
reg [15:0] tx_crc16_r;
reg [3:0] tx_crc16_s;
reg [7:0] crc16_addr;
......@@ -83,7 +83,8 @@ module crc16_xmodem#(
reg tx_out_stb_r;
reg tx_out_stb_r2;
reg tx_gen_bsy;
reg tx_rdy_r; // registered stuffer ready
// reg tx_run; // during CRC generation/output
wire tx_crc16_next; // calculate next CRC16
wire [15:0] crc16_table; // valid at tx_crc16_s[3]
......@@ -95,30 +96,42 @@ module crc16_xmodem#(
assign tx_busy = tx_busy_r;
assign txd_out = txd_out_r;
assign tx_in_rdy = tx_in_rdy_r;
// assign tx_in_rdy = tx_in_rdy_r;
assign tx_in_rdy = tx_in_rdy_r && tx_rdy_r; // && tx_run;
assign tx_out_stb = tx_out_stb_r;
always @(posedge mclk) begin
tx_rdy_r <= tx_rdy;
// TODO: Clean up from tx_busy_r
if (mrst) tx_in_rdy_r <= 0;
else if (tx_start || tx_crc16_s[0]) tx_in_rdy_r <= 1; // tx_crc16_next
// else if (tx_start || tx_crc16_s[0]) tx_in_rdy_r <= 1; // tx_crc16_next
else if (tx_start || tx_crc16_next) tx_in_rdy_r <= 1; // tx_crc16_next
else if (tx_in_stb || tx_over) tx_in_rdy_r <= 0;
/// else if (!tx_busy_r) tx_in_rdy_r <= 1;
if (mrst) tx_gen_bsy <= 0;
else if (tx_in_stb) tx_gen_bsy <= 1;
else if (tx_out_stb_r) tx_gen_bsy <= 0;
if (mrst) tx_pre_crc <= 0;
else if (tx_start) tx_pre_crc <= 0;
else if (tx_over) tx_pre_crc <= 1;
if (mrst) tx_pre_crc <= 0;
else if (tx_start || tx_crc_out[0]) tx_pre_crc <= 0;
else if (tx_over) tx_pre_crc <= 1;
if (mrst) tx_crc_out[0] <= 0;
else if (tx_start) tx_crc_out[0] <= 0;
else if (tx_pre_crc && !tx_gen_bsy) tx_crc_out[0] <= 1;
if (mrst) tx_crc_out[0] <= 0;
else if (tx_start || tx_out_stb_r) tx_crc_out[0] <= 0;
else if (tx_pre_crc && !tx_gen_bsy && !tx_crc_out[1]) tx_crc_out[0] <= 1;
if (mrst) tx_crc_out[1] <= 0;
else if (tx_start) tx_crc_out[1] <= 0;
// else if (tx_crc_out[0] && tx_out_stb_r) tx_crc_out[1] <= 1;
else if (tx_out_stb_r) tx_crc_out[1] <= tx_crc_out[0];
// if (mrst) tx_run <= 0;
// else if (tx_start) tx_run <= 1;
// else if (tx_crc_out[1] && tx_out_stb_r) tx_run <= 0;
if (mrst) tx_crc_out[1] <= 0;
else if (tx_start) tx_crc_out[1] <= 0;
else if (tx_crc_out[0] && tx_out_stb_r) tx_crc_out <= 2'h1;
tx_crc_out_d <= tx_crc_out;
......@@ -143,11 +156,12 @@ module crc16_xmodem#(
if (tx_in_stb) txd_in_r <= txd_in;
tx_stb_crc_l2 <= tx_stb_crc_l;
// tx_stb_crc_l2 <= tx_stb_crc_l;
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_stb_crc_l2) tx_busy_r <= 0;
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
// else if (tx_stb_crc_l2) tx_busy_r <= 0;
else if (tx_out_stb_r && tx_crc_out[1]) tx_busy_r <= 0;
if (tx_start) tx_crc16_r <= INITIAL_CRC16;
else if (tx_crc16_next) tx_crc16_r <= tx_crc16_w;
......
......@@ -106,11 +106,6 @@ module sens_103993 #(
parameter NUMLANES = 3,
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
// parameter LVDS_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
// parameter LVDS_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
// parameter LVDS_FIFO_DEPTH = 4,
// parameter LVDS_FIFO_START = 7,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
......@@ -126,10 +121,6 @@ module sens_103993 #(
parameter PXD_IOSTANDARD = "LVCMOS18", // 1.8V single-ended
parameter PXD_SLEW = "SLOW",
parameter PXD_CAPACITANCE = "DONT_CARE",
// parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
// parameter PXD_CLK_DIV_BITS = 4,
// ,parameter STATUS_ALIVE_WIDTH = 4
// parameter SENSIO_SKIP_BITS = 8, // number of bits in line skip counter
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
......@@ -194,6 +185,9 @@ module sens_103993 #(
input extif_rst
);
wire[7:0]debug_UART_CLK_DIV = CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = RX_DEBOUNCE; // 6,
wire dvalid_w;
reg dvalid_r;
// wire vact_w;
......@@ -461,7 +455,8 @@ module sens_103993 #(
.dvalid (dvalid_w), // output
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r[23:0]), // input[23:0]
// .dly_data (data_r[23:0]), // input[23:0]
.dly_data (data_r), // input[23:0]
.set_idelay ({NUMLANES{set_idelays}}),// input[2:0]
.ld_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
......
......@@ -46,13 +46,14 @@ module sens_103993_deser10(
);
reg [9:0] sr;
reg [9:0] dout_r;
wire [9:0] pre_sr;
assign dout = dout_r;
assign pre_sr = {sr[8:0], din};
always @(posedge pclk10) begin
sr <= {sr[8:0], din};
sr <= pre_sr;
end
always @(posedge pclk) begin
dout_r <= sr;
dout_r <= pre_sr;
end
endmodule
......@@ -435,6 +435,17 @@ module sensor_channel#(
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter UART_START_FRAME_BYTE = 'h8E,
parameter UART_END_FRAME_BYTE = 'hAE,
parameter UART_ESCAPE_BYTE = 'h9E,
parameter UART_REPLACED_START_FRAME_BYTE = 'h81,
parameter UART_REPLACED_END_FRAME_BYTE = 'hA1,
parameter UART_REPLACED_ESCAPE_BYTE = 'h91,
parameter UART_INITIAL_CRC16 = 16'h1d0f,
parameter UART_CLK_DIV = 217,
parameter UART_RX_DEBOUNCE = 60,
parameter UART_EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
`endif
`ifdef DEBUG_RING
......@@ -1219,7 +1230,18 @@ module sensor_channel#(
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.PXD_CAPACITANCE (PXD_CAPACITANCE)
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.START_FRAME_BYTE (UART_START_FRAME_BYTE),// 'h8E),
.END_FRAME_BYTE (UART_END_FRAME_BYTE), // 'hAE),
.ESCAPE_BYTE (UART_ESCAPE_BYTE), // 'h9E),
.REPLACED_START_FRAME_BYTE(UART_REPLACED_START_FRAME_BYTE), // 'h81),
.REPLACED_END_FRAME_BYTE (UART_REPLACED_END_FRAME_BYTE), // 'hA1),
.REPLACED_ESCAPE_BYTE (UART_REPLACED_ESCAPE_BYTE), // 'h91),
.INITIAL_CRC16 (UART_INITIAL_CRC16), // 16'h1d0f),
.CLK_DIV (UART_CLK_DIV), // 217),
.RX_DEBOUNCE (UART_RX_DEBOUNCE), // 60),
.EXTIF_MODE (UART_EXTIF_MODE) // 1)
) sens_103993_i (
.pclk (pclk), // output
.locked_pclk (locked_pclk), // output
......@@ -1234,8 +1256,10 @@ module sensor_channel#(
.status_start (sens_phys_status_start), // input
// .trigger_mode (trigger_mode), // input
.ext_sync (trig), // input
.sns_dp (sns_dp[2:0]), // input[2:0]
.sns_dn (sns_dn[2:0]), // input[2:0]
// .sns_dp (sns_dp[2:0]), // input[2:0]
// .sns_dn (sns_dn[2:0]), // input[2:0]
.sns_dp (sns_dp), // input[2:0]
.sns_dn (sns_dn), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.sns_gp2 (sns_dn74[6]), // inout
......
......@@ -455,6 +455,17 @@ module sensors393 #(
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter UART_START_FRAME_BYTE = 'h8E,
parameter UART_END_FRAME_BYTE = 'hAE,
parameter UART_ESCAPE_BYTE = 'h9E,
parameter UART_REPLACED_START_FRAME_BYTE = 'h81,
parameter UART_REPLACED_END_FRAME_BYTE = 'hA1,
parameter UART_REPLACED_ESCAPE_BYTE = 'h91,
parameter UART_INITIAL_CRC16 = 16'h1d0f,
parameter UART_CLK_DIV = 217,
parameter UART_RX_DEBOUNCE = 60,
parameter UART_EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
`endif
......@@ -959,7 +970,16 @@ module sensors393 #(
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
.UART_START_FRAME_BYTE (UART_START_FRAME_BYTE),// 'h8E),
.UART_END_FRAME_BYTE (UART_END_FRAME_BYTE), // 'hAE),
.UART_ESCAPE_BYTE (UART_ESCAPE_BYTE), // 'h9E),
.UART_REPLACED_START_FRAME_BYTE (UART_REPLACED_START_FRAME_BYTE), // 'h81),
.UART_REPLACED_END_FRAME_BYTE (UART_REPLACED_END_FRAME_BYTE), // 'hA1),
.UART_REPLACED_ESCAPE_BYTE (UART_REPLACED_ESCAPE_BYTE), // 'h91),
.UART_INITIAL_CRC16 (UART_INITIAL_CRC16), // 16'h1d0f),
.UART_CLK_DIV (UART_CLK_DIV), // 217),
.UART_RX_DEBOUNCE (UART_RX_DEBOUNCE), // 60),
.UART_EXTIF_MODE (UART_EXTIF_MODE), // 1)
`endif
`ifdef DEBUG_RING
......
......@@ -82,6 +82,9 @@ module serial_103993#(
output [7:0] recv_data
);
wire[7:0]debug_UART_CLK_DIV = CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = RX_DEBOUNCE; // 6,
wire [ 7:0] xmit_fifo_out;
wire [ 1:0] xmit_fifo_re_regen;
wire [10:0] xmit_fifo_waddr;
......@@ -132,31 +135,33 @@ module serial_103993#(
assign extif_rq_w = packet_ready_seq && !extif_run && !packet_over_seq;
assign xmit_any_data = extif_run ? xmit_extif_data : xmit_fifo_out;
assign xmit_stb_any = extif_run ? xmit_stb_seq : xmit_stb_fifo;
assign xmit_stb_any = extif_run ? xmit_stb_seq : xmit_stb_fifo;
assign xmit_over = extif_run ? xmit_over_seq : xmit_over_fifo;
assign xmit_start_out_fifo = xmit_run && !xmit_run_d;
assign xmit_start_out_seq = extif_run && !extif_run_d;
assign xmit_start_out = xmit_start_out_fifo || xmit_start_out_seq;
assign pre_tx_stb = !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
// assign pre_tx_stb = !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
// TODO: is !xmit_stb_d needed?
assign pre_tx_stb = !xmit_stb_any && !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
assign xmit_busy = xmit_busy_r;
// assign packet_sent = xmit_over && !xmit_over_d;
always @(posedge mclk) begin
xmit_busy_r <= uart_tx_busy || stuffer_busy_d || xmit_pend || xmit_run || extif_run;
if (mrst || xmit_rst) xmit_pend <= 0;
else if (xmit_start) xmit_pend <= 1;
else if (xmit_start_out_fifo) xmit_pend <= 0;
if (mrst || xmit_rst) xmit_pend <= 0;
else if (xmit_start) xmit_pend <= 1;
else if (xmit_start_out_fifo) xmit_pend <= 0;
if (mrst || xmit_rst) xmit_run <= 0;
else if (xmit_pend && !xmit_run && extif_run) xmit_run <= 1;
else if (xmit_done) xmit_run <= 0; // no need to condition with xmit_run
if (mrst || xmit_rst) xmit_run <= 0;
else if (xmit_pend && !xmit_run && !extif_run) xmit_run <= 1;
else if (xmit_done) xmit_run <= 0; // no need to condition with xmit_run
// else if (!stuffer_busy && !xmit_fifo_nempty) xmit_run <= 0; // no need to condition with xmit_run
xmit_run_d <= xmit_run && !mrst && !xmit_rst;
if (mrst || extif_rst) extif_run <= 0;
if (mrst || extif_rst) extif_run <= 0;
else if (!xmit_run && !xmit_pend && extif_rq_w) extif_run <= 1;
else if (xmit_done) extif_run <= 0; // no need to condition with xmit_run
else if (xmit_done) extif_run <= 0; // no need to condition with xmit_run
extif_run_d <= extif_run && !mrst && !extif_rst;
xmit_stb_d <= xmit_stb_any;
......
......@@ -68,6 +68,9 @@ module serial_fslp #(
output rx_packet_run, // run received packet
output rx_packet_done // finished receiving packet (last 2 bytes - crc16)
);
wire[7:0]debug_UART_CLK_DIV = CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = RX_DEBOUNCE; // 6,
wire [7:0] uart_txd;
wire [7:0] uart_rxd;
wire uart_tx_stb;
......
......@@ -49,7 +49,7 @@ module serial_stuffer #(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input packet_run, // goes inactive after last txd_in_stb
input tx_in_stb,
input tx_in_stb, // data strobe from crc16
input [7:0] txd_in,
output stuffer_rdy, // stuffer ready to accept tx_in_stb
input uart_rdy, // uart ready to accept byte
......@@ -62,6 +62,7 @@ module serial_stuffer #(
reg [1:0] stuffer_start;
reg stuffer_finsh;
reg packet_trailer;
reg pre_trailer;
reg packet_header;
reg escape_cyc0;
reg [2:0] escape_cyc1;
......@@ -69,60 +70,81 @@ module serial_stuffer #(
reg [7:0] txd_in_r;
reg [2:0] tx_in_stb_r;
reg [2:0] need_escape;
reg [1:0] byte_out_set; //
reg [3:0] byte_out_set; //
wire byte_out_stb; // ==byte_out_set[1]
reg [7:0] uart_txd_r;
reg tx_dav;
reg tx_dav; // for sending data to uart
reg copy_in_byte;
reg stuffer_rdy_r;
wire pre_stuffer_start_w;
wire proc_next_in_byte; // when txd_in_r contains new data and uart is ready to accept one
wire proc_trailer; // when trailer and uart is ready to accept one
reg txd_in_r_full; // txd_in_r contains data
wire use_txd_in_r;
wire set_trailer;
assign stuffer_busy = stuffer_busy_r;
assign uart_stb = uart_stb_r;
assign uart_txd = uart_txd_r;
assign stuffer_rdy = stuffer_rdy_r;
assign pre_stuffer_start_w = ~stuffer_busy_r & packet_run;
assign use_txd_in_r = byte_out_stb && !escape_cyc0 && !packet_header && !packet_trailer;
assign proc_next_in_byte = txd_in_r_full && uart_rdy && ! (|tx_in_stb_r) && !(|byte_out_set);
assign proc_trailer = packet_trailer && uart_rdy && ! (|tx_in_stb_r) && !(|byte_out_set) && !stuffer_finsh;
assign set_trailer = !pre_trailer && !packet_trailer && !escape_cyc0 && !packet_run && stuffer_busy_r; //
assign byte_out_stb = byte_out_set[1];
always @(posedge mclk) begin
stuffer_start <= {stuffer_start[0], ~stuffer_busy_r & packet_run};
if (mrst || !stuffer_busy_r) txd_in_r_full <= 0;
else if (tx_in_stb) txd_in_r_full <= 1;
else if (use_txd_in_r) txd_in_r_full <= 0;
stuffer_start <= {stuffer_start[0], pre_stuffer_start_w};
if (mrst) stuffer_busy_r <= 0;
else if (stuffer_start[0]) stuffer_busy_r <= 1;
else if (packet_trailer && uart_stb_r) stuffer_busy_r <= 0;
if (mrst) stuffer_rdy_r <= 0;
else if (stuffer_start || tx_in_stb || stuffer_finsh) stuffer_rdy_r <= 0;
else if (byte_out_set[1] && (!escape_cyc0)) stuffer_rdy_r <= 1;
if (mrst) stuffer_busy_r <= 0;
else if (pre_stuffer_start_w) stuffer_busy_r <= 1;
else if (packet_trailer && uart_stb_r) stuffer_busy_r <= 0;
if (mrst || !stuffer_busy_r) stuffer_rdy_r <= 0;
else if (stuffer_start[0]) stuffer_rdy_r <= 1;
else if (tx_in_stb || stuffer_finsh) stuffer_rdy_r <= 0;
else if (use_txd_in_r) stuffer_rdy_r <= 1;
else if (!stuffer_busy_r) stuffer_rdy_r <= 1; //*
tx_in_stb_r <= {tx_in_stb_r[1:0],tx_in_stb};
tx_in_stb_r <= {tx_in_stb_r[1:0], proc_next_in_byte}; // tx_in_stb};
if (tx_in_stb) txd_in_r <= txd_in;
if (tx_in_stb_r[0]) need_escape <= {
(txd_in_r == START_FRAME_BYTE)? 1'b1 : 1'b0,
// if (tx_in_stb_r[0]) need_escape <= {
if (tx_in_stb_r[0] && !escape_cyc0) need_escape <= {
(txd_in_r == ESCAPE_BYTE)? 1'b1 : 1'b0,
(txd_in_r == END_FRAME_BYTE)? 1'b1 : 1'b0,
(txd_in_r == ESCAPE_BYTE)? 1'b1 : 1'b0};
(txd_in_r == START_FRAME_BYTE)? 1'b1 : 1'b0};
if (mrst) escape_cyc0 <= 0;
else if (tx_in_stb_r[1]) escape_cyc0 <= |need_escape;
else if (uart_stb_r) escape_cyc0 <= 0;
// else if (tx_in_stb_r[1]) escape_cyc0 <= |need_escape;
// else if (uart_stb_r) escape_cyc0 <= 0;
else if (tx_in_stb_r[1]) escape_cyc0 <= |need_escape && !escape_cyc0;
if (mrst) escape_cyc1 <= 0;
// else if (uart_stb_r) escape_cyc1 <= {3{escape_cyc0}} & need_escape;
else if (uart_stb_r) escape_cyc1 <= {3{escape_cyc0}} & need_escape;
if (mrst) byte_out_set <= 0;
else byte_out_set <= {byte_out_set[0], tx_in_stb_r[2] | stuffer_start[1] | stuffer_finsh};
else byte_out_set <= {byte_out_set[2:0], tx_in_stb_r[2] | stuffer_start[1] | stuffer_finsh};
if (mrst) packet_header <= 0;
else if (stuffer_start[1]) packet_header <= 1;
else if (byte_out_set[1]) packet_header <= 0;
else if (byte_out_stb) packet_header <= 0;
if (!stuffer_busy_r) pre_trailer <= 0;
else if (byte_out_stb) pre_trailer <= set_trailer;
if (!stuffer_busy_r) packet_trailer <= 0;
else if (!packet_run) packet_trailer <= 1;
stuffer_finsh <= stuffer_rdy_r && stuffer_busy_r && packet_trailer; // !packet_run
else if (uart_stb_r) packet_trailer <= pre_trailer;
stuffer_finsh <= proc_trailer; // stuffer_rdy_r && stuffer_busy_r && packet_trailer; // !packet_run
copy_in_byte <= !need_escape && !packet_header && !packet_trailer;
copy_in_byte <= !(|need_escape) && !packet_header && !packet_trailer;
if (byte_out_set[1]) uart_txd_r <=
if (byte_out_stb) uart_txd_r <=
({8{packet_header}} & START_FRAME_BYTE) |
({8{packet_trailer}} & END_FRAME_BYTE) |
({8{escape_cyc0}} & ESCAPE_BYTE) |
......@@ -132,7 +154,7 @@ module serial_stuffer #(
({8{copy_in_byte}} & txd_in_r);
if (mrst) tx_dav <= 0;
else if (byte_out_set[1]) tx_dav <= 1;
else if (byte_out_stb) tx_dav <= 1;
else if (uart_stb_r) tx_dav <= 0;
if (mrst) uart_stb_r <= 0;
......
......@@ -56,9 +56,12 @@ module simul_103993_serializer#(
localparam PERIOD = 1000.0/PCLK_FREQ_MHZ;
wire [9:0] dclocks;
assign #(PERIOD/20) dclocks[9:0] = ~{dclocks[8:0], pclk};
/*
// dclocks[8:0] - OK, but
// dclocks[9] was delayed twice from dclocks[8]
assign #(PERIOD/20) dclocks[9:0] = ~{dclocks[8:0], pclk};
*/
assign #(PERIOD/20) dclocks[0] = pclk;
assign #(PERIOD/20) dclocks[1] = dclocks[0];
assign #(PERIOD/20) dclocks[2] = dclocks[1];
......@@ -69,7 +72,7 @@ module simul_103993_serializer#(
assign #(PERIOD/20) dclocks[7] = dclocks[6];
assign #(PERIOD/20) dclocks[8] = dclocks[7];
assign #(PERIOD/20) dclocks[9] = dclocks[8];
*/
wire clk10 = ^dclocks[9:0];
reg [9:0] r_red;
reg [9:0] r_green;
......@@ -93,7 +96,7 @@ module simul_103993_serializer#(
always @ (posedge clk10) begin
clk_r <= {clk_r[0], pclk};
set_sr <= clk_r[0] && !clk_r[0];
set_sr <= clk_r[0] && !clk_r[1];
if (set_sr) begin
sr_red <= r_red;
sr_green <= r_green;
......
......@@ -49,7 +49,7 @@ module simul_boson640#(
parameter FP = 52, // FP_BP = 52+50
parameter VSW = 87 // with telemetry, in eows
)(
input mrst,
input mrst,// active low
input single,
input ext_sync,
output [15:0] pxd,
......@@ -97,7 +97,7 @@ module simul_boson640#(
localparam LSTATE_BP = 4'b1000;
assign pclk = ~pclk_r;
assign uart_out = uart_in && !mrst;
assign uart_out = uart_in; // && mrst;
assign last_line = (frame_state == FSTATE_OUT) && (line_cntr == 0);
assign last_in_line = (line_state == LSTATE_BP) && (pix_cntr == 0);
assign start_frame = ((frame_state == FSTATE_IDLE) || (last_line && last_in_line)) && (!single | (ext_sync && !ext_sync_d));
......@@ -111,17 +111,17 @@ module simul_boson640#(
$readmemh({`ROOTPATH,DATA_FILE},sensor_data);
end
always #(CLK_PERIOD/2) pclk_r <= mrst ? 1'b0: ~pclk_r;
always #(CLK_PERIOD/2) pclk_r <= mrst ? ~pclk_r : 1'b0;
always @ (posedge pclk_r) begin
dvalid_r <= pre_dav && !mrst;
dvalid_r <= pre_dav && mrst;
if (mrst) ext_sync_d <= 0;
else ext_sync_d <= ext_sync;
if (!mrst) ext_sync_d <= 0;
else ext_sync_d <= ext_sync;
// frame_state_d <=frame_state;
if (mrst) begin
if (!mrst) begin
frame_state <= FSTATE_IDLE;
end else begin
case (frame_state)
......@@ -151,7 +151,7 @@ module simul_boson640#(
endcase
end
if (mrst) begin
if (!mrst) begin
line_state <= 0;
pix_cntr <= HSW - 1;
end else if (start_line) begin
......
......@@ -1996,7 +1996,7 @@ assign axi_grst = axi_rst_pre;
`endif
`ifdef LWIR
`else
`else // used for BOSON too
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
......@@ -2043,6 +2043,53 @@ assign axi_grst = axi_rst_pre;
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
`elsif BOSON
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK0 (HISPI_DELAY_CLK0),
.HISPI_DELAY_CLK1 (HISPI_DELAY_CLK1),
.HISPI_DELAY_CLK2 (HISPI_DELAY_CLK2),
.HISPI_DELAY_CLK3 (HISPI_DELAY_CLK3),
.HISPI_MMCM0 (HISPI_MMCM0),
.HISPI_MMCM1 (HISPI_MMCM1),
.HISPI_MMCM2 (HISPI_MMCM2),
.HISPI_MMCM3 (HISPI_MMCM3),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.UART_START_FRAME_BYTE (UART_START_FRAME_BYTE),// 'h8E),
.UART_END_FRAME_BYTE (UART_END_FRAME_BYTE), // 'hAE),
.UART_ESCAPE_BYTE (UART_ESCAPE_BYTE), // 'h9E),
.UART_REPLACED_START_FRAME_BYTE(UART_REPLACED_START_FRAME_BYTE), // 'h81),
.UART_REPLACED_END_FRAME_BYTE (UART_REPLACED_END_FRAME_BYTE), // 'hA1),
.UART_REPLACED_ESCAPE_BYTE (UART_REPLACED_ESCAPE_BYTE), // 'h91),
.UART_INITIAL_CRC16 (UART_INITIAL_CRC16), // 16'h1d0f),
.UART_CLK_DIV (UART_CLK_DIV), // 217),
.UART_RX_DEBOUNCE (UART_RX_DEBOUNCE), // 60),
.UART_EXTIF_MODE (UART_EXTIF_MODE), // 1)
`endif
`ifdef DEBUG_RING
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY),
......@@ -2158,7 +2205,9 @@ assign axi_grst = axi_rst_pre;
.debug_di (debug_ring[1]) // input
`endif
);
wire[7:0]debug_UART_CLK_DIV = UART_CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = UART_RX_DEBOUNCE; // 6,
// AFI1 (AXI_HP1) signals - write channels only
wire [31:0] afi1_awaddr; // output[31:0]
wire afi1_awvalid; // output
......