Commits · fbf5fddb7220575954ad3de66f7c3ec4cdbe8a4d · Elphel / x393

02 Apr, 2015 1 commit
- adding measurement of DQ_ODELAY vs DQS_ODELAY · fbf5fddb
  Andrey Filippov authored Apr 02, 2015
  
  fbf5fddb
22 Mar, 2015 1 commit
- debugging command/address timing adjustment · e4dae58e
  Andrey Filippov authored Mar 22, 2015
  
  e4dae58e
20 Mar, 2015 1 commit
- chaneged handling of the shared parameters, added defaults and saving modified... · 1902d5ce
  Andrey Filippov authored Mar 20, 2015
```
chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
```
  1902d5ce
18 Mar, 2015 1 commit
- testing hardware, adding related code · 7a0b9347
  Andrey Filippov authored Mar 18, 2015
  
  7a0b9347
11 Mar, 2015 1 commit
- implemented help for task based on functions documentation · fad107cb
  Andrey Filippov authored Mar 11, 2015
  
  fad107cb
08 Mar, 2015 1 commit
- more verilog tasks converted to python · f7c03985
  Andrey Filippov authored Mar 08, 2015
  
  f7c03985