Commits · ebdb638ec59be8d9f56a800f45f7a1bc5596c8bf · Elphel / x393

14 Mar, 2016 1 commit
- Modified DDR memory calibration to reduce occasional failures · ea63654a
  Andrey Filippov authored Mar 14, 2016
  
  ea63654a
11 Nov, 2015 1 commit
- got first images from mt9f002 · 81da483f
  Andrey Filippov authored Nov 11, 2015
  
  81da483f
11 Oct, 2015 1 commit
- added hwmon command · 0a729a6a
  Andrey Filippov authored Oct 11, 2015
  
  0a729a6a
12 Sep, 2015 1 commit
- Fixed some errors in old memory controller modules · ccbfbf84
  Andrey Filippov authored Sep 12, 2015
  
  ccbfbf84
31 Aug, 2015 1 commit
- hardware debugging/bug fixing · 77c76c3b
  Andrey Filippov authored Aug 31, 2015
  
  77c76c3b
29 Aug, 2015 2 commits
- Added Python modules to setup memory channels for sensors and compressors, rtc · 9a17dbfa
  Andrey Filippov authored Aug 29, 2015
  
  9a17dbfa
- added more Python modules to control hardware, some bug fixes · d9f09d9d
  Andrey Filippov authored Aug 29, 2015
  
  d9f09d9d
06 May, 2015 1 commit
- Debugging hardware, added functionality to detect cache-related problems · cdf97c98
  Andrey Filippov authored May 06, 2015
  
  cdf97c98
05 May, 2015 1 commit
- Fixed handling AXI write responce channel - both in work and simulation... · 988095ef
  Andrey Filippov authored May 05, 2015
```
Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
```
  988095ef
04 May, 2015 1 commit
- debugging qith hardware · 9b16ac66
  Andrey Filippov authored May 04, 2015
  
  9b16ac66
03 May, 2015 1 commit
- methods for testing membridge module · 079114c1
  Andrey Filippov authored May 03, 2015
  
  079114c1