Cleaning up the code, adding provisions for multiple solutions for the same phase - this will be the case at higher clock frequencies

 in two files

finalized DQS input delay vs clock phase adjustment, combined all current results together as a function of the clock phase

chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file

module to keep global (Verilog) parameters, self-modified code to include pre-defines fro PyDev to be happy)