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Elphel
x393
Commits
d9f09d9df5d3cf5270b4c5aa62cae019fccc3daf
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x393
py393
.project
03 Mar, 2015
1 commit
creating Python program to pass Verilog parameters to Python FPGA tests
· 4c3995d6
Andrey Filippov
authored
Mar 03, 2015
4c3995d6