Commits · d9f09d9df5d3cf5270b4c5aa62cae019fccc3daf · Elphel / x393

29 Aug, 2015 1 commit
- added more Python modules to control hardware, some bug fixes · d9f09d9d
  Andrey Filippov authored Aug 29, 2015
  
  d9f09d9d
23 Aug, 2015 1 commit
- simulating multiple simultanerous sesnor/compressor channels · 225fccd0
  Andrey Filippov authored Aug 23, 2015
  
  225fccd0
12 Aug, 2015 1 commit
- more simulation - histograms, transfer over saxi, writing to video memory · daf46a7e
  Andrey Filippov authored Aug 12, 2015
  
  daf46a7e
09 Aug, 2015 1 commit
- Adding vignetting correction module · 3d7d6607
  Andrey Filippov authored Aug 09, 2015
  
  3d7d6607
06 Aug, 2015 1 commit
- simulating/bug fixing · bcaa005d
  Andrey Filippov authored Aug 06, 2015
  
  bcaa005d
05 Aug, 2015 1 commit
- continue with test fixture · 9afdf9d6
  Andrey Filippov authored Aug 05, 2015
  
  9afdf9d6
03 Aug, 2015 1 commit
- contunue with test tasks · 1de3d68f
  Andrey Filippov authored Aug 03, 2015
  
  1de3d68f
02 Aug, 2015 1 commit
- writing sensor simulation code · c153c326
  Andrey Filippov authored Aug 02, 2015
  
  c153c326
01 Aug, 2015 1 commit
- making previous simulation tasks run on the full x393 code · 3af47156
  Andrey Filippov authored Aug 01, 2015
  
  3af47156
23 Jul, 2015 1 commit
- made tools run successfully, no timing errors · 8b0a0f11
  Andrey Filippov authored Jul 23, 2015
  
  8b0a0f11
20 Jul, 2015 1 commit
- continue fighting with Vivado tools · 0524b747
  Andrey Filippov authored Jul 20, 2015
  
  0524b747
19 Jul, 2015 1 commit
- trying synthesis · 50c837f9
  Andrey Filippov authored Jul 19, 2015
  
  50c837f9
18 Jul, 2015 1 commit
- Implemented clock management, entered pads physical constraints · 16513305
  Andrey Filippov authored Jul 18, 2015
  
  16513305
17 Jul, 2015 2 commits
- adding synchronization and logger modules · 2585b4af
  Andrey Filippov authored Jul 17, 2015
  
  2585b4af
- adding synchronization and logger modules · 69e5938a
  Andrey Filippov authored Jul 17, 2015
  
  69e5938a
16 Jul, 2015 1 commit
- connecting sensor and compressor signals to the memory controller · 299231f6
  Andrey Filippov authored Jul 16, 2015
  
  299231f6
14 Jul, 2015 1 commit
- connecting sensor subsystem to the top module · 6f36f6d1
  Andrey Filippov authored Jul 14, 2015
  
  6f36f6d1
13 Jul, 2015 1 commit
- creating a top module for all four sensor channels · 3023d860
  Andrey Filippov authored Jul 13, 2015
  
  3023d860
12 Jul, 2015 2 commits
- Increase command adderss space, modified address map to fit sesnor/compressor related registers · cadd05c1
  Andrey Filippov authored Jul 12, 2015
  
  cadd05c1
- Changed 'author' to full name · 41babf8a
  Andrey Filippov authored Jul 12, 2015
  
  41babf8a
06 Jul, 2015 1 commit
- Fixed teplate error in the headers · 93e8aa42
  Andrey Filippov authored Jul 06, 2015
  
  93e8aa42
24 Jun, 2015 1 commit
- porting jpeg/jp4 compressor · db90602d
  Andrey Filippov authored Jun 24, 2015
  
  db90602d
06 May, 2015 1 commit
- Debugging hardware, added functionality to detect cache-related problems · cdf97c98
  Andrey Filippov authored May 06, 2015
  
  cdf97c98
29 Apr, 2015 1 commit
- connecting new modules for membridge to top module and test fixture · 890bad1c
  Andrey Filippov authored Apr 29, 2015
  
  890bad1c
28 Apr, 2015 1 commit
- Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp · 7a0fa46b
  Andrey Filippov authored Apr 28, 2015
  
  7a0fa46b
22 Apr, 2015 1 commit
- bug fixes in Verilog code · 286a6494
  Andrey Filippov authored Apr 22, 2015
  
  286a6494
20 Mar, 2015 1 commit
- chaneged handling of the shared parameters, added defaults and saving modified... · 1902d5ce
  Andrey Filippov authored Mar 20, 2015
```
chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
```
  1902d5ce
28 Feb, 2015 1 commit
- working on synthesis with Vivado tools · 05378ee7
  Andrey Filippov authored Feb 28, 2015
  
  05378ee7
25 Feb, 2015 1 commit
- more bugs fixing with simulation · 7b13989a
  Andrey Filippov authored Feb 25, 2015
  
  7b13989a
23 Feb, 2015 1 commit
- before adding extra register layer between channel buffers outputs and memory controller · 943fc4a1
  Andrey Filippov authored Feb 23, 2015
  
  943fc4a1
22 Feb, 2015 2 commits
- debugging after modifications · 7614ead5
  Andrey Filippov authored Feb 22, 2015
  
  7614ead5
- re-organized top structure · ad0351ef
  Andrey Filippov authored Feb 22, 2015
  
  ad0351ef
20 Feb, 2015 1 commit
- added another channel for testing - tile write · a445ef42
  Andrey Filippov authored Feb 20, 2015
  
  a445ef42
18 Feb, 2015 1 commit
- testing read memory as rectangular tiles · cd7cb395
  Andrey Filippov authored Feb 18, 2015
  
  cd7cb395
14 Feb, 2015 1 commit
- debugging scanline read memory access · 8f79e6f7
  Andrey Filippov authored Feb 14, 2015
  
  8f79e6f7
13 Feb, 2015 1 commit
- debugging, more corrections, tested block write through PIO channel 1 · f4751492
  Andrey Filippov authored Feb 13, 2015
  
  f4751492
10 Feb, 2015 1 commit
- continue simulation, moved some code to includes after modifying VDT to... · f9e935af
  Andrey Filippov authored Feb 10, 2015
```
continue simulation, moved some code to includes after modifying VDT to support project-relative includes
```
  f9e935af
09 Feb, 2015 1 commit
- started simulation · 99191719
  Andrey Filippov authored Feb 09, 2015
  
  99191719
08 Feb, 2015 1 commit
- Working on simulation testbench · 575da59a
  Andrey Filippov authored Feb 08, 2015
  
  575da59a