Commits · c505535cf199229fda4c5879cb43a908bb51b675 · Elphel / x393

30 May, 2015 1 commit
- added wrappers for block RAM in TDP mode (each port with R+W) · c505535c
  Andrey Filippov authored May 30, 2015
  
  c505535c
29 May, 2015 4 commits
- transferring data between clk anc clk2x domains · 4aceda5f
  Andrey Filippov authored May 29, 2015
  
  4aceda5f
- typo fix · cad9a46e
  Andrey Filippov authored May 29, 2015
  
  cad9a46e
- parametrized (9-36 bit wide) module wrapper utilizing parity bits to extend data width · b6281d7d
  Andrey Filippov authored May 29, 2015
  
  b6281d7d
- module to convert 16-bit data to 8 bit using piecewise-linear table conversion · a670c623
  Andrey Filippov authored May 29, 2015
  
  a670c623
21 May, 2015 1 commit
- working on the sensor input FIFO to compensate for clock domains crossing · a6ac2cd2
  Andrey Filippov authored May 21, 2015
  
  a6ac2cd2
19 May, 2015 1 commit
- working on sensor channel · 6021159e
  Andrey Filippov authored May 19, 2015
  
  6021159e
15 May, 2015 1 commit
- working on files realted to sensor channels, added frame sequences to... · 6b2c4c47
  Andrey Filippov authored May 15, 2015
```
working on files realted to sensor channels, added frame sequences to mcntrl_linear_rw.v and mcntrl_tiled_rw.v
```
  6b2c4c47
06 May, 2015 1 commit
- Debugging hardware, added functionality to detect cache-related problems · cdf97c98
  Andrey Filippov authored May 06, 2015
  
  cdf97c98
05 May, 2015 2 commits
- Fixed handling AXI write responce channel - both in work and simulation... · 988095ef
  Andrey Filippov authored May 05, 2015
```
Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
```
  988095ef
- Fixed ddr3 -> system memory transfer · 0fda102e
  Andrey Filippov authored May 05, 2015
  
  0fda102e
04 May, 2015 4 commits
- made membridge work in system -> videobuffer mode · 59a577c9
  Andrey Filippov authored May 04, 2015
  
  59a577c9
- debugging qith hardware · 9b16ac66
  Andrey Filippov authored May 04, 2015
  
  9b16ac66
- removed *py393/dbg not to update them ater each re-run · cd414e1d
  Andrey Filippov authored May 04, 2015
  
  cd414e1d
- removed *.pickle not to update them ater each re-run · b2c0f94c
  Andrey Filippov authored May 04, 2015
  
  b2c0f94c
03 May, 2015 3 commits
- preparing for testing membridge module on the target system · bda74800
  Andrey Filippov authored May 03, 2015
  
  bda74800
- methods for testing membridge module · 079114c1
  Andrey Filippov authored May 03, 2015
  
  079114c1
- moved afi-related tasks here from the top simulation test fixture · 54115ba0
  Andrey Filippov authored May 03, 2015
  
  54115ba0
30 Apr, 2015 2 commits
- more debuggin/simulation of the membridge module · 7274dadc
  Andrey Filippov authored Apr 30, 2015
  
  7274dadc
- simulating/debugging · 8b79e3f7
  Andrey Filippov authored Apr 30, 2015
  
  8b79e3f7
29 Apr, 2015 1 commit
- connecting new modules for membridge to top module and test fixture · 890bad1c
  Andrey Filippov authored Apr 29, 2015
  
  890bad1c
28 Apr, 2015 1 commit
- Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp · 7a0fa46b
  Andrey Filippov authored Apr 28, 2015
  
  7a0fa46b
27 Apr, 2015 4 commits
- renamed for consistency · caf85bde
  Andrey Filippov authored Apr 27, 2015
  
  caf85bde
- renamed for consistency · 6708307d
  Andrey Filippov authored Apr 27, 2015
  
  6708307d
- added missing files · bb5c2299
  Andrey Filippov authored Apr 27, 2015
  
  bb5c2299
- converted channel buffers to configurable width · e79823db
  Andrey Filippov authored Apr 27, 2015
  
  e79823db
26 Apr, 2015 2 commits
- implemented axi_hp_rd simulation module · 307cff59
  Andrey Filippov authored Apr 26, 2015
  
  307cff59
- working on simulation modules for axi_hp · 6bafd2c5
  Andrey Filippov authored Apr 26, 2015
  
  6bafd2c5
24 Apr, 2015 2 commits
- added method to generate parameters summary · e878fd92
  Andrey Filippov authored Apr 24, 2015
  
  e878fd92
- Added acquired data for off-line testing · 586b8213
  Andrey Filippov authored Apr 24, 2015
  
  586b8213
22 Apr, 2015 3 commits
- added link to vdt-plugin in README.md · 53e40753
  Andrey Filippov authored Apr 22, 2015
  
  53e40753
- bug fixes in Verilog code · 286a6494
  Andrey Filippov authored Apr 22, 2015
  
  286a6494
- Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing · c8b52324
  Andrey Filippov authored Apr 22, 2015
  
  c8b52324
21 Apr, 2015 5 commits
- minor adjustments · 1d2f08b7
  Andrey Filippov authored Apr 21, 2015
  
  1d2f08b7
- removed obsolete code · decdd057
  Andrey Filippov authored Apr 21, 2015
  
  decdd057
- co-debugging simulation with hardware tests to make them match · 1e313eb7
  Andrey Filippov authored Apr 21, 2015
  
  1e313eb7
- modulte to adjust timing to actual hadrware · ea23bda4
  Andrey Filippov authored Apr 21, 2015
  
  ea23bda4
- timing parameters generated by the hardware testing · 72f01b6d
  Andrey Filippov authored Apr 21, 2015
  
  72f01b6d
20 Apr, 2015 1 commit
- bug fixes · 8729da71
  Andrey Filippov authored Apr 20, 2015
  
  8729da71
17 Apr, 2015 1 commit
- more testing · f92b8da3
  Andrey Filippov authored Apr 17, 2015
  
  f92b8da3