Commits · c2b29afdf7e58573ea59d84824f6a35e53655e49 · Elphel / x393

06 May, 2015 1 commit
- Debugging hardware, added functionality to detect cache-related problems · cdf97c98
  Andrey Filippov authored May 06, 2015
  
  cdf97c98
05 May, 2015 2 commits
- Fixed handling AXI write responce channel - both in work and simulation... · 988095ef
  Andrey Filippov authored May 05, 2015
```
Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
```
  988095ef
- Fixed ddr3 -> system memory transfer · 0fda102e
  Andrey Filippov authored May 05, 2015
  
  0fda102e
04 May, 2015 1 commit
- made membridge work in system -> videobuffer mode · 59a577c9
  Andrey Filippov authored May 04, 2015
  
  59a577c9
03 May, 2015 1 commit
- preparing for testing membridge module on the target system · bda74800
  Andrey Filippov authored May 03, 2015
  
  bda74800
30 Apr, 2015 2 commits
- more debuggin/simulation of the membridge module · 7274dadc
  Andrey Filippov authored Apr 30, 2015
  
  7274dadc
- simulating/debugging · 8b79e3f7
  Andrey Filippov authored Apr 30, 2015
  
  8b79e3f7
22 Apr, 2015 2 commits
- bug fixes in Verilog code · 286a6494
  Andrey Filippov authored Apr 22, 2015
  
  286a6494
- Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing · c8b52324
  Andrey Filippov authored Apr 22, 2015
  
  c8b52324
21 Apr, 2015 2 commits
- minor adjustments · 1d2f08b7
  Andrey Filippov authored Apr 21, 2015
  
  1d2f08b7
- co-debugging simulation with hardware tests to make them match · 1e313eb7
  Andrey Filippov authored Apr 21, 2015
  
  1e313eb7
18 Mar, 2015 1 commit
- testing hardware, adding related code · 7a0b9347
  Andrey Filippov authored Mar 18, 2015
  
  7a0b9347
15 Mar, 2015 1 commit
- porting delay scan/adjustment functions from the eddr3 Python code · 6ff31a13
  Andrey Filippov authored Mar 15, 2015
  
  6ff31a13
01 Mar, 2015 1 commit
- working with Xilinx ISE/Vivado to synthesize and P&R the design · 0466926c
  Andrey Filippov authored Mar 01, 2015
  
  0466926c
28 Feb, 2015 1 commit
- working on synthesis with Vivado tools · 05378ee7
  Andrey Filippov authored Feb 28, 2015
  
  05378ee7
25 Feb, 2015 2 commits
- more fixes · df69d555
  Andrey Filippov authored Feb 25, 2015
  
  df69d555
- more bugs fixing with simulation · 7b13989a
  Andrey Filippov authored Feb 25, 2015
  
  7b13989a
23 Feb, 2015 1 commit
- before adding extra register layer between channel buffers outputs and memory controller · 943fc4a1
  Andrey Filippov authored Feb 23, 2015
  
  943fc4a1
22 Feb, 2015 3 commits
- more simulatin/bug fixing · d2db8c14
  Andrey Filippov authored Feb 22, 2015
  
  d2db8c14
- debugging after modifications · 7614ead5
  Andrey Filippov authored Feb 22, 2015
  
  7614ead5
- re-organized top structure · ad0351ef
  Andrey Filippov authored Feb 22, 2015
  
  ad0351ef
20 Feb, 2015 2 commits
- created and tested cmd_encod_tiled_32_wr.v - tiles with 32-byte columns · f35bb39d
  Andrey Filippov authored Feb 20, 2015
  
  f35bb39d
- added another channel for testing - tile write · a445ef42
  Andrey Filippov authored Feb 20, 2015
  
  a445ef42
19 Feb, 2015 1 commit
- more debugging tile read · c8076f57
  Andrey Filippov authored Feb 19, 2015
  
  c8076f57
18 Feb, 2015 1 commit
- testing read memory as rectangular tiles · cd7cb395
  Andrey Filippov authored Feb 18, 2015
  
  cd7cb395
17 Feb, 2015 1 commit
- debugging larger frames write/read · 864a8593
  Andrey Filippov authored Feb 17, 2015
  
  864a8593
16 Feb, 2015 2 commits
- more debugging · 7c5ab53d
  Andrey Filippov authored Feb 16, 2015
  
  7c5ab53d
- modified scanline mode to work with SDRAM page crossing (by splitting in 2), debugging read mode · e3d5b404
  Andrey Filippov authored Feb 16, 2015
  
  e3d5b404
15 Feb, 2015 1 commit
- ran some tests with TEST_SCANLINE_WRITE, fixed some bugs · 547054f6
  Andrey Filippov authored Feb 15, 2015
  
  547054f6
14 Feb, 2015 1 commit
- debugging scanline read memory access · 8f79e6f7
  Andrey Filippov authored Feb 14, 2015
  
  8f79e6f7
13 Feb, 2015 3 commits
- split top level test fixture file into separate includes with tasks · cbbd4ed1
  Andrey Filippov authored Feb 13, 2015
  
  cbbd4ed1
- more debugging by simulation, bug fixing · 38d73a7b
  Andrey Filippov authored Feb 13, 2015
  
  38d73a7b
- debugging, more corrections, tested block write through PIO channel 1 · f4751492
  Andrey Filippov authored Feb 13, 2015
  
  f4751492
12 Feb, 2015 1 commit
- debugging, more corrections, tested write levelling/buffer reading · bb237119
  Andrey Filippov authored Feb 12, 2015
  
  bb237119
11 Feb, 2015 1 commit
- debugging/simulation · d899569e
  Andrey Filippov authored Feb 11, 2015
  
  d899569e
10 Feb, 2015 2 commits
- more simulation · dde1725e
  Andrey Filippov authored Feb 10, 2015
  
  dde1725e
- tested register writes, status generation, routing and reading · 9f629dc4
  Andrey Filippov authored Feb 10, 2015
  
  9f629dc4
09 Feb, 2015 1 commit
- started simulation · 99191719
  Andrey Filippov authored Feb 09, 2015
  
  99191719