x393:bda7480082a43947ee86ab7016d58457064965c2 commitshttps://git.elphel.com/Elphel/x393/commits/bda7480082a43947ee86ab7016d58457064965c22015-05-03T06:06:39Zhttps://git.elphel.com/Elphel/x393/commit/bda7480082a43947ee86ab7016d58457064965c2preparing for testing membridge module on the target system2015-05-03T06:06:39ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/079114c15b253da97eec09f25625ecbb3fa17340methods for testing membridge module2015-05-03T06:05:33ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/54115ba0611f5972def94a7f43eb309747be313dmoved afi-related tasks here from the top simulation test fixture2015-05-03T06:04:10ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/7274dadc6cd269b0a258863240a0d65882a4b1bemore debuggin/simulation of the membridge module2015-04-30T18:30:42ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8b79e3f777678e214137e01c8e1acd2760243335simulating/debugging2015-04-30T06:40:50ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/890bad1c72c728d8c88cee8427f78ef2a3dbe298connecting new modules for membridge to top module and test fixture2015-04-29T05:36:52ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/7a0fa46b359712ff7e41afd28093949af51df28cWorking on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp2015-04-28T23:12:35ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/caf85bdeb224cc5d7e0714e07ca8ab339e4d85e9renamed for consistency2015-04-27T05:03:59ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/6708307dad9654658917bc74179ec77d7a1834ebrenamed for consistency2015-04-27T05:02:31ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/bb5c2299f5fd0e341fe65bd44c978aae07c40023added missing files2015-04-27T01:24:31ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e79823dbc2043b1422cbdb70bbb3b3e15e120623converted channel buffers to configurable width2015-04-27T01:16:56ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/307cff59c4d630fc3f5281f0f96c04824608b225implemented axi_hp_rd simulation module2015-04-26T19:55:43ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/6bafd2c50c900abf353ba3ce1f4294669ca5dceeworking on simulation modules for axi_hp2015-04-26T05:43:04ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e878fd921e79143a24467ec24df61330ce636acfadded method to generate parameters summary2015-04-24T18:40:33ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/586b821327bd45569267fa5a6afce6ee9d8d78edAdded acquired data for off-line testing2015-04-24T18:39:00ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/53e407530fc2263acb34f6abc8ac83d559175f6badded link to vdt-plugin in README.md2015-04-22T22:15:47ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/286a6494e98fc8a6bfbf4d2cc25c59059d42a3bfbug fixes in Verilog code2015-04-22T22:10:44ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/c8b52324624c3604f0809148ccde37e6a058abdcModified write module to support variable 'sel' input, adjustedg hardware to ...2015-04-22T06:24:51ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/1d2f08b7fcdde69ae15ec38ee7e29ffc6747f49dminor adjustments2015-04-21T03:51:02ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/decdd05763f04070b7be8e365826af5675d019d5removed obsolete code2015-04-21T03:10:28ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/1e313eb7e07fe29d0740d0ff191c7863026b7c43co-debugging simulation with hardware tests to make them match2015-04-21T03:09:46ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/ea23bda453fa8b8f0843727510a5b8f8f9aeef11modulte to adjust timing to actual hadrware2015-04-21T03:08:06ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/72f01b6da2d416d98bdecc7bc97b978d6bd15c81timing parameters generated by the hardware testing2015-04-21T03:06:12ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8729da71f3949af58f35be41469db6f07aa5274abug fixes2015-04-20T14:37:40ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/f92b8da30f73137f4d440c8d8cb2729e1305cd84more testing2015-04-17T14:55:51ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/5fc7988039b5f41690fff6fcd84672064b5bf3e0desting, debugging, cleaning up2015-04-17T01:03:02ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/4aaf6074e267959878f02748058c1e71007f19c8more debugging2015-04-15T05:49:14ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/9b43bdd6250001816735fcf9802dccb06551a11cCleaning up the code, adding provisions for multiple solutions for the same...2015-04-14T07:23:59ZAndrey Filippovandrey@elphel.comCleaning up the code, adding provisions for multiple solutions for the same phase - this will be the case at higher clock frequencies
https://git.elphel.com/Elphel/x393/commit/588817622e711e8e5a14a516c10b41fce87db341cleaned up, before multiple branches in dqs and cmda2015-04-09T16:49:45ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/45d1f6b7acd81f50b4ba5dc450d366899bae09ccAdding selection correct branch of read/write delays (considering full/half c...2015-04-09T03:49:26ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8ffbbc62a8104052670846e2f51cb3146cde4f23added save/load state with pickle2015-04-07T06:51:01ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/82800325a547c5cf19c2654b9b357e141984f690made the whole program to run automatically from the command file2015-04-07T03:04:39ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/5d662c48d1a91aefbc32baf5d70e5e0771968b3cinput file to run initilaaization, adjustment and saving parameters automatic...2015-04-07T03:04:00ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/5449c194751ad37f18404f56d0e3ed34b4712e4cadded measurement/adjustment of WE, RAS, CAS delays2015-04-07T00:49:38ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/494d6c95cdda81d7637dc799e9b960d315667298Implemented measurement/processing of address/bank lines output delays2015-04-06T04:55:59ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/c9bb19f14a62b8a86144c422fe2125744af7b401Split py393/x393_mcntrl_adjust.py2015-04-06T04:54:51ZAndrey Filippovandrey@elphel.com in two fileshttps://git.elphel.com/Elphel/x393/commit/a700414610b188a0c537dc1abd61f7589f8fbdf5some cleanup, added command that runs full set of measurement/adjustment func...2015-04-04T01:18:38ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/4a9e4b55075c748ba205e40d935062f16538f83dadding LMA processing of DQ_ODELAY vs DQS_ODELAY2015-04-02T06:24:57ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/fbf5fddb7220575954ad3de66f7c3ec4cdbe8a4dadding measurement of DQ_ODELAY vs DQS_ODELAY2015-04-02T01:57:39ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/1417d17e699d3f1257ca54df061534f6b9dcecc1finalized DQS input delay vs clock phase adjustment, combined all current...2015-04-01T04:27:51ZAndrey Filippovandrey@elphel.comfinalized DQS input delay vs clock phase adjustment, combined all current results together as a function of the clock phase