- 03 Nov, 2015 1 commit
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Andrey Filippov authored
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- 01 Nov, 2015 1 commit
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Andrey Filippov authored
Made several modifications to fix all timing violations to run compressor @250MHz - 1.0 Gigapixel/sec in JP4 mode
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- 31 Oct, 2015 1 commit
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Andrey Filippov authored
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- 27 Oct, 2015 1 commit
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Andrey Filippov authored
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- 13 Oct, 2015 1 commit
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Andrey Filippov authored
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- 12 Oct, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 11 Oct, 2015 1 commit
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Andrey Filippov authored
added simuilation modules for frequency multiplication/division, fractional period delays, started parallel12 -> HiSPi packetized SP converter
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- 10 Oct, 2015 1 commit
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Andrey Filippov authored
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- 09 Oct, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 06 Oct, 2015 1 commit
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Andrey Filippov authored
started modification of the i2c sequencer to support SMIA registers (2 bytes address, >=2 bytes of data) and register read
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- 29 Sep, 2015 1 commit
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Andrey Filippov authored
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