Commits · 70528b01b8c78b8a0361c75070f4c2224819176a · Elphel / x393

07 Sep, 2015 3 commits
- got (some) compressed image data to the circbuf · 70528b01
  Andrey Filippov authored Sep 07, 2015
  
  70528b01
- done with testing sensor channles, starting debugging compressor · 7a4e8e08
  Andrey Filippov authored Sep 07, 2015
  
  7a4e8e08
- continue hardware debugging, fixed gamma and histograms · 608bcbd9
  Andrey Filippov authored Sep 07, 2015
  
  608bcbd9
06 Sep, 2015 2 commits
- removed extra debug signals, fixed tools settings after vdt update · da2d549d
  Andrey Filippov authored Sep 06, 2015
  
  da2d549d
- continue hardware debugging · cbed019c
  Andrey Filippov authored Sep 06, 2015
  
  cbed019c
04 Sep, 2015 3 commits
- debugging with debug ring · 3bff174e
  Andrey Filippov authored Sep 04, 2015
  
  3bff174e
- hardware debugging/testing · ed32ff53
  Andrey Filippov authored Sep 04, 2015
  
  ed32ff53
- adding modules to read/write debug data over the daisy-chained ring · 09a3a7cd
  Andrey Filippov authored Sep 04, 2015
  
  09a3a7cd
31 Aug, 2015 1 commit
- hardware debugging/bug fixing · 77c76c3b
  Andrey Filippov authored Aug 31, 2015
  
  77c76c3b
29 Aug, 2015 4 commits
- More Python code for testing hardware · 72068ae7
  Andrey Filippov authored Aug 29, 2015
  
  72068ae7
- Added Python modules to setup memory channels for sensors and compressors, rtc · 9a17dbfa
  Andrey Filippov authored Aug 29, 2015
  
  9a17dbfa
- marked correspondence to Python in Verilog testbench · 2adfbae2
  Andrey Filippov authored Aug 29, 2015
  
  2adfbae2
- added more Python modules to control hardware, some bug fixes · d9f09d9d
  Andrey Filippov authored Aug 29, 2015
  
  d9f09d9d
28 Aug, 2015 3 commits
- working on Python code for testing hardware · b13c86d4
  Andrey Filippov authored Aug 28, 2015
  
  b13c86d4
- Added Python module to control compressor · 53d28e32
  Andrey Filippov authored Aug 28, 2015
  
  53d28e32
- Added Python module to program AXI HP multiplexer for compressed image data · cedb78c5
  Andrey Filippov authored Aug 28, 2015
  
  cedb78c5
27 Aug, 2015 10 commits
- adding more Python methods to test new hardware functionality · f35b9514
  Andrey Filippov authored Aug 27, 2015
  
  f35b9514
- adding comments for matching Python methods · a04debc6
  Andrey Filippov authored Aug 27, 2015
  
  a04debc6
- adding module to program camera GPIO signals · f208a23c
  Andrey Filippov authored Aug 27, 2015
  
  f208a23c
- adding module to program inter-camera synchronization · dd82cc8a
  Andrey Filippov authored Aug 27, 2015
  
  dd82cc8a
- started Python module to control sensors/compressors related functionality · 0e3d3df3
  Andrey Filippov authored Aug 27, 2015
  
  0e3d3df3
- Updated Python code, added some missing comments · 35ff16ab
  Andrey Filippov authored Aug 27, 2015
  
  35ff16ab
- added text output of compressed data for matching · 57a04d4d
  Andrey Filippov authored Aug 27, 2015
  
  57a04d4d
- added attribute set before bitstream generation - set_property... · 1a24c7a8
  Andrey Filippov authored Aug 27, 2015
```
added attribute set before bitstream generation - set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]"
```
  1a24c7a8
- Started bug fixing after hardware testing · 4a69ce71
  Andrey Filippov authored Aug 27, 2015
  
  4a69ce71
- added separate file for 32-bit hex FPGA version that can be read by software · dbab453b
  Andrey Filippov authored Aug 27, 2015
  
  dbab453b
23 Aug, 2015 4 commits
- continue multichannel simulation, fixed bug in cmprs_afi_mux - second one · 170c7b59
  Andrey Filippov authored Aug 23, 2015
  
  170c7b59
- continue multichannel simulation, fixed bug in cmprs_afi_mux · 8aa8c82f
  Andrey Filippov authored Aug 23, 2015
  
  8aa8c82f
- continue multichannel simulation · 24011430
  Andrey Filippov authored Aug 23, 2015
  
  24011430
- simulating multiple simultanerous sesnor/compressor channels · 225fccd0
  Andrey Filippov authored Aug 23, 2015
  
  225fccd0
19 Aug, 2015 1 commit

Finished simulation/testing of a single-channel... · a500d197

Andrey Filippov authored Aug 19, 2015

Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation

a500d197

18 Aug, 2015 2 commits
- more simulating cmprs_afi_mux · df351507
  Andrey Filippov authored Aug 18, 2015
  
  df351507
- simulating cmprs_afi_mux · cd341af8
  Andrey Filippov authored Aug 18, 2015
  
  cd341af8
17 Aug, 2015 1 commit
- Matched simulation (agianst 353) through all the compression modules · c71eec74
  Andrey Filippov authored Aug 17, 2015
  
  c71eec74
16 Aug, 2015 1 commit
- continue debugging · a5d68f54
  Andrey Filippov authored Aug 16, 2015
  
  a5d68f54
15 Aug, 2015 5 commits
- Fixed errors to match 353 simulation in DC subtraction and DCT calculation modules · 22f7ceaa
  Andrey Filippov authored Aug 15, 2015
  
  22f7ceaa
- debugging color conversion · f18a13be
  Andrey Filippov authored Aug 15, 2015
  
  f18a13be
- continiuing co-simulation with 353 code, verified martching data to the compressor input · de641880
  Andrey Filippov authored Aug 15, 2015
  
  de641880
- includes to pass initialization parameters to block RAM primitives · 947d1d99
  Andrey Filippov authored Aug 15, 2015
  
  947d1d99
- added Python scripts to create ram initialization for simulation shortcut · 1182a36e
  Andrey Filippov authored Aug 15, 2015
  
  1182a36e