x393:1902d5ce1e404a90441674ee106e80501d6adc10 commitshttps://git.elphel.com/Elphel/x393/commits/1902d5ce1e404a90441674ee106e80501d6adc102015-03-20T06:07:00Zhttps://git.elphel.com/Elphel/x393/commit/1902d5ce1e404a90441674ee106e80501d6adc10chaneged handling of the shared parameters, added defaults and saving modifie...2015-03-20T06:07:00ZAndrey Filippovandrey@elphel.comchaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
https://git.elphel.com/Elphel/x393/commit/e6b5bfc1b2fef28837a4e9d633c735689dc14792module to keep global (Verilog) parameters, self-modified code to include...2015-03-20T06:05:43ZAndrey Filippovandrey@elphel.commodule to keep global (Verilog) parameters, self-modified code to include pre-defines fro PyDev to be happy)
https://git.elphel.com/Elphel/x393/commit/7a0b9347ebe85eba48e76421255943ee5a8e77d9testing hardware, adding related code2015-03-18T04:59:01ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e6bc87ee5fe8b0cb054b86c689fe566519b3896emore porting dealy scan/adjust functionality from eddr32015-03-15T07:08:23ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/aabad99e4758c8df6bb02623f8ff4814367022a8added module with ported delays scan/adjustment functions2015-03-15T04:32:15ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/6ff31a1390f5d752909850179acf3867bb9e607cporting delay scan/adjustment functions from the eddr3 Python code2015-03-15T04:30:50ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/652c47ec2d107be126df973b161b5dfcbde4f4b2Description of the memory controller clocks and programmable delays2015-03-15T04:29:38ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8df14818b49fc8533911b2b94febb8b628f36827more hardware tests2015-03-13T02:22:01ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/49288bf210bb27ea05089aac419b880e49474247debugging hardware, added re filters for parameters and macros2015-03-12T20:48:41ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/9326e2420317ccb529214c4cbbf83900b246cf21debugging2015-03-12T06:44:56ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/27a6599b69dcb394996795c94a997b019868cf08working on hardware testing, added utility functions to load bitstream and us...2015-03-12T03:24:03ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/fad107cb2ca57d575d0bdcf7091def89e6752192implemented help for task based on functions documentation2015-03-11T05:48:46ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e6868ded7eea0b7f8281cac4c74da753a2df5594implemented @file in the test_mcntrl.py command line2015-03-10T05:33:32ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/f7c039856cce093f4cb94895355c64434d815788more verilog tasks converted to python2015-03-08T05:37:27ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8de61d312ef16a4c818258fc941bb6fb8d5a7bdbnext snapshot, implemented more expression types in parameter parsing2015-03-07T18:46:36ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/21e45a9976b1094e94d7c808c8ead12d63a7dce2more code converted from Verilog to Python2015-03-05T06:17:28ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/eba342eb85c65470dd63b71c9e2899b912285403continue with python hardware test code2015-03-05T02:17:26ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/63ff28196f1947fbe67394d2772bfb0a3a241fefworking on Python code for hardware testing2015-03-04T08:09:15ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/4c3995d60e80de575bd9e252ff345eb2adca56cbcreating Python program to pass Verilog parameters to Python FPGA tests2015-03-03T03:25:45ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/0466926cc72c1177ca3da46a75dcebddcc62b0f3working with Xilinx ISE/Vivado to synthesize and P&R the design2015-03-01T05:00:39ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/05378ee794495b9e30e0b6080f489a9965804b0eworking on synthesis with Vivado tools2015-02-28T07:25:56ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/df69d5558e5626cc06d45eac44459e10bf472d81more fixes2015-02-25T03:23:54ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/7b13989a8a8018e9a2769009a13fc6194fd7a03dmore bugs fixing with simulation2015-02-25T01:48:12ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/943fc4a1d621ee4d34700788e5793d04baf08c1bbefore adding extra register layer between channel buffers outputs and memory...2015-02-23T20:45:44ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/d2db8c14bec3351c03a3baa4d17b900ca6e2cb03more simulatin/bug fixing2015-02-22T22:36:15ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/7614ead578505a40e9ef9beccfdf2a0e261d50afdebugging after modifications2015-02-22T08:01:48ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/ad0351ef12f2a368a8571ff148b3feb689075980re-organized top structure2015-02-22T04:46:27ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/f35bb39d9ba6f256b1ad0d1352db07fb4a86d5f4created and tested cmd_encod_tiled_32_wr.v - tiles with 32-byte columns2015-02-20T08:02:51ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/a445ef42b7671646d5bf50bf1bdd0a8929048a95added another channel for testing - tile write2015-02-20T01:33:38ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/31a6b9715722780461c54f89e30bb6af82d36173added tile write (column order)2015-02-20T01:32:46ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/22beced0c4bbdf847b025f676cf533af099f3154version of the tile read with 32-byte wide columns - easier timing with vario...2015-02-19T06:36:59ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/c8076f572e43eae002305a58db9cf64f4862cf1emore debugging tile read2015-02-19T02:45:31ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/cd7cb395f7797c32e6e795f6fc4757d33df03633testing read memory as rectangular tiles2015-02-18T07:45:42ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/864a8593223776161994e48e0d596d3ccfeedaa5debugging larger frames write/read2015-02-17T05:02:00ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/7c5ab53db81117a3564f78b0ee4f19e0920be285more debugging2015-02-16T09:35:59ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e3d5b404f83c6f3bce0048429664a13ffc64a9eemodified scanline mode to work with SDRAM page crossing (by splitting in 2), ...2015-02-16T00:46:00ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/547054f6d1fbe52dd9008fc0305d7a925edeaf4aran some tests with TEST_SCANLINE_WRITE, fixed some bugs2015-02-15T06:06:00ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8f79e6f735ce8bb851bd3257f4eb67198b53b463debugging scanline read memory access2015-02-14T17:09:47ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/cbbd4ed1ed3d1fa6c3a15c945e086acfaae6d93bsplit top level test fixture file into separate includes with tasks2015-02-13T20:31:02ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/38d73a7b8ce1dd2ed92d6b06c121f9858c90a62cmore debugging by simulation, bug fixing2015-02-13T19:15:46ZAndrey Filippovandrey@elphel.com