x393:1563de24d94e62859afb309373aec2aafe3cf177 commitshttps://git.elphel.com/Elphel/x393/commits/1563de24d94e62859afb309373aec2aafe3cf1772015-01-11T23:23:17Zhttps://git.elphel.com/Elphel/x393/commit/1563de24d94e62859afb309373aec2aafe3cf177converting eddr3 to the x393 project2015-01-11T23:23:17ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/b80c19f8586208285674597c9615b229e423366amodified include path2014-11-02T05:17:51ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/d0cdb65450694c7dfbe2a0d819a6e96de3cbc11dModifications for Icarus Verilog2014-06-24T04:23:22ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/2d6f9609dca8c80333711e8ec4a690d77d52b94aAdded link to the blog post2014-06-24T04:22:36ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/09784ed72d6d6eef5031dc4448e6dd1dca78e91beye pattern tests at 400MHz2014-06-15T08:32:28ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/d9e0dd239f59f169bafceaf989ad29ae30e9812epatch to work with Icarus Verilog simulator2014-06-15T07:32:58ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/52b99362e63618a4a5d2eba24d181321760ca01fadded glbl.v2014-06-15T07:02:52ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e00b15e355f64ed81d9e697bef9d44b4626f0fd7code to align bit delays on random data2014-06-14T07:18:21ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/2ac46e216ade15709c39bf146990ac9e051342e9implemented read leveling, eye measurement for DDR3 on random data2014-06-12T23:43:29ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/f6b8d427e8e322bf861030520bb0a34411314355adjusted dealys, tested write/read leveling, write and read blocks2014-06-11T22:59:05ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/f2c019cd1bfe8925be96af38a43080706274b7d5working with hardware2014-06-11T20:16:47ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/780f735993bc3c76aa0dbb570fdc8081430ae159debugging hardware2014-06-11T09:45:47ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/5450474d46c20a0125f6ea5ab08ccf63d99bde0edebugging hardware2014-06-11T01:28:15ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/393faaf1a9563a560edbf666a6b23077becdf951'Translating' test fixture from Verilog to Python for testing the actual hard...2014-06-11T01:27:36ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/ef3e06aaa8d0700b896c68d32e583e54dd2acd59renamed directory2014-06-08T01:32:07ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/896e116ae03ba9b73a447977bbf2b26a93982a22renamed directory2014-06-08T01:29:57ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/1fc578b2aa340adaa786c2e8e20e2b31192dba99added headers2014-06-08T01:29:08ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/7e44243bdb65cd14dde32fe8123a292c7efd72aaorganized new/debug files2014-06-08T01:18:41ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/cd437a8f4fc1a174ee0326a8cf84bb5c46331e5aMerge branch 'master' of github.com:Elphel/eddr32014-06-07T23:30:53ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/c57b67b83bf788ba0679bdcd36715c51c5fae40adebugging hardware2014-06-07T23:30:25ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/2f4f51916f1d5a4870c8b6a278c156b06512ebcbCreate README.md2014-06-07T01:48:28ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/cd3ccb58e093301dbfd636180d91345d7e3901c1troubleshooting lack of DONE during loading of the bitfile2014-06-07T01:43:44ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/6176aa7b8006c1e6afce86cd7df3b4fb799f887efixed DCI and ODT for all tested modes2014-06-02T18:31:15ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/0102893157ed741d44e5997973e4f94c697367a5bug fixes, implemented read pattern test, so all major DDR3 modes are tested:...2014-06-01T23:25:52ZAndrey Filippovandrey@elphel.combug fixes, implemented read pattern test, so all major DDR3 modes are tested: write and read leveling, write and read
https://git.elphel.com/Elphel/x393/commit/46cf253d17ff32325165a05793b9209b52d3bfa3added configuration for ISE, timing constraints for Vivado2014-06-01T01:38:08ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/0bd9ef33fa55e6a8991848a435ea28b2005bae93change DM* I/O standard to SSTL152014-05-31T06:46:31ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/37d1bee7fed0fc1e065e2d3c2e0b28cec5f72ca1added pause bit to make sequneces more compact, implemented ddr3 read block test2014-05-31T06:29:57ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/d9b14b007027f84d46e75d931cc9e51389689322added 16-bit shift register2014-05-31T06:28:31ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/c72a52a9b632e33e788a18374f9c6286200bc4e4added warnings for illegal fine delays2014-05-31T06:26:54ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/4bacb90a01662f5419bbbed4b1a1652a615eb6c8write leveling done, working on write buffer2014-05-30T07:46:41ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/1b719ff1ffc9b5c161120db831a7d0a777989e1eworking with DDR3 model2014-05-28T07:20:38ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/105bffcd935263466a54a1d1da963670037e8bc6added Micron DDR3 model, modified to work with Icarus, modified Icarus to avo...2014-05-28T07:19:48ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/3d67d687e8e8fb2afb119ed3f2ecbd31e3cc8937debugging, next snapshot2014-05-28T04:39:12ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8b1e18d43f6c5b46d8bf97458eb5145e733b0b6cdebugging2014-05-22T21:32:48ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/c8904b67b498b43c14d6cf001193861f7873f14eadded modules, simulating2014-05-22T08:13:04ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/5034058e2100d2fd1c869d71570ac7933308f326added modules to test ddrc phy over axi read/write2014-05-20T05:46:01ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/03bce2116120a77afd9ea143454754a1b3a609fdaddint top level module to test pasrt of ddr controller2014-05-19T07:12:39ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/f57364b82f1af779f214088446b1c2134eb30fadaxi interface files added2014-05-18T06:22:08ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/bd8a0bceebba010ccd804bd86350440ade1577f8working of ddr command sequencer2014-05-17T19:55:48ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/d67337790c5c577d7b95435222b810344d9949e9just a snapshot2014-05-17T00:03:11ZAndrey Filippovandrey@elphel.com