Commits · 116c9ce225d238e89e3d2163798bf486c8489586 · Elphel / x393

05 Jun, 2016 1 commit
- Modified headers to work with doxverilog2.5/doxygen1.7.0 · 00e7a575
  Andrey Filippov authored Jun 05, 2016
  
  00e7a575
05 May, 2016 1 commit
- multiple changes, synchronizing simulation with hardware · 82e11ec7
  Andrey Filippov authored May 05, 2016
  
  82e11ec7
15 Nov, 2015 1 commit
- debugging JP4 mode, got correct JP4 image · 78d2e067
  Andrey Filippov authored Nov 15, 2015
  
  78d2e067
11 Nov, 2015 1 commit
- got first images from mt9f002 · 81da483f
  Andrey Filippov authored Nov 11, 2015
  
  81da483f
08 Nov, 2015 4 commits
- Typo in file headers · 72d1c082
  Andrey Filippov authored Nov 08, 2015
  
  72d1c082
- More file headers editing · 691ae8a4
  Andrey Filippov authored Nov 08, 2015
  
  691ae8a4
- added 'Additional permission under GNU GPL version 3 section 7' to each file header · 1392ef16
  Andrey Filippov authored Nov 08, 2015
  
  1392ef16
- more simulation with HiSPi sensors · 31e4c348
  Andrey Filippov authored Nov 08, 2015
  
  31e4c348
01 Nov, 2015 1 commit
- Made several modifications to fix all timing violations to run compressor... · 4ca48f7b
  Andrey Filippov authored Nov 01, 2015
```
Made several modifications to fix all timing violations to run compressor @250MHz - 1.0 Gigapixel/sec in JP4 mode
```
  4ca48f7b
31 Oct, 2015 1 commit
- Tested compressor version w/o 2x clock, fixed errors found · 30fae557
  Andrey Filippov authored Oct 31, 2015
  
  30fae557
22 Oct, 2015 1 commit
- modifying histograms module to avoid use of the double pixel frequency clock · cfdcac60
  Andrey Filippov authored Oct 22, 2015
  
  cfdcac60
21 Oct, 2015 1 commit
- processing frame syn before previous frame is finished (fast forward, skipping memory transactions) · 59774283
  Andrey Filippov authored Oct 21, 2015
  
  59774283
18 Oct, 2015 1 commit
- simulating/bug fixing · 75f18826
  Andrey Filippov authored Oct 18, 2015
  
  75f18826
29 Aug, 2015 1 commit
- More Python code for testing hardware · 72068ae7
  Andrey Filippov authored Aug 29, 2015
  
  72068ae7
12 Aug, 2015 1 commit
- more simulation - histograms, transfer over saxi, writing to video memory · daf46a7e
  Andrey Filippov authored Aug 12, 2015
  
  daf46a7e
07 Aug, 2015 1 commit
- more simulating/debugging of sensor interface modules · aa331d14
  Andrey Filippov authored Aug 07, 2015
  
  aa331d14
06 Aug, 2015 1 commit
- simulating/bug fixing · bcaa005d
  Andrey Filippov authored Aug 06, 2015
  
  bcaa005d
05 Aug, 2015 1 commit
- continue with test fixture · 9afdf9d6
  Andrey Filippov authored Aug 05, 2015
  
  9afdf9d6
02 Aug, 2015 1 commit
- writing sensor simulation code · c153c326
  Andrey Filippov authored Aug 02, 2015
  
  c153c326
01 Aug, 2015 1 commit
- making previous simulation tasks run on the full x393 code · 3af47156
  Andrey Filippov authored Aug 01, 2015
  
  3af47156
12 Jul, 2015 1 commit
- Changed 'author' to full name · 41babf8a
  Andrey Filippov authored Jul 12, 2015
  
  41babf8a
06 Jul, 2015 1 commit
- Fixed teplate error in the headers · 93e8aa42
  Andrey Filippov authored Jul 06, 2015
  
  93e8aa42
12 Mar, 2015 1 commit
- working on hardware testing, added utility functions to load bitstream and use GPIO for debugging · 27a6599b
  Andrey Filippov authored Mar 12, 2015
  
  27a6599b
12 Feb, 2015 1 commit
- debugging, more corrections, tested write levelling/buffer reading · bb237119
  Andrey Filippov authored Feb 12, 2015
  
  bb237119
10 Feb, 2015 1 commit
- continue simulation, moved some code to includes after modifying VDT to... · f9e935af
  Andrey Filippov authored Feb 10, 2015
```
continue simulation, moved some code to includes after modifying VDT to support project-relative includes
```
  f9e935af
09 Feb, 2015 1 commit
- started simulation · 99191719
  Andrey Filippov authored Feb 09, 2015
  
  99191719
08 Feb, 2015 1 commit
- Working on simulation testbench · 575da59a
  Andrey Filippov authored Feb 08, 2015
  
  575da59a