Commits · 0466926cc72c1177ca3da46a75dcebddcc62b0f3 · Elphel / x393

01 Mar, 2015 1 commit
- working with Xilinx ISE/Vivado to synthesize and P&R the design · 0466926c
  Andrey Filippov authored Mar 01, 2015
  
  0466926c
28 Feb, 2015 1 commit
- working on synthesis with Vivado tools · 05378ee7
  Andrey Filippov authored Feb 28, 2015
  
  05378ee7
25 Feb, 2015 2 commits
- more fixes · df69d555
  Andrey Filippov authored Feb 25, 2015
  
  df69d555
- more bugs fixing with simulation · 7b13989a
  Andrey Filippov authored Feb 25, 2015
  
  7b13989a
23 Feb, 2015 1 commit
- before adding extra register layer between channel buffers outputs and memory controller · 943fc4a1
  Andrey Filippov authored Feb 23, 2015
  
  943fc4a1
22 Feb, 2015 3 commits
- more simulatin/bug fixing · d2db8c14
  Andrey Filippov authored Feb 22, 2015
  
  d2db8c14
- debugging after modifications · 7614ead5
  Andrey Filippov authored Feb 22, 2015
  
  7614ead5
- re-organized top structure · ad0351ef
  Andrey Filippov authored Feb 22, 2015
  
  ad0351ef
20 Feb, 2015 3 commits
- created and tested cmd_encod_tiled_32_wr.v - tiles with 32-byte columns · f35bb39d
  Andrey Filippov authored Feb 20, 2015
  
  f35bb39d
- added another channel for testing - tile write · a445ef42
  Andrey Filippov authored Feb 20, 2015
  
  a445ef42
- added tile write (column order) · 31a6b971
  Andrey Filippov authored Feb 20, 2015
  
  31a6b971
19 Feb, 2015 2 commits
- version of the tile read with 32-byte wide columns - easier timing with various tile heights · 22beced0
  Andrey Filippov authored Feb 19, 2015
  
  22beced0
- more debugging tile read · c8076f57
  Andrey Filippov authored Feb 19, 2015
  
  c8076f57
18 Feb, 2015 1 commit
- testing read memory as rectangular tiles · cd7cb395
  Andrey Filippov authored Feb 18, 2015
  
  cd7cb395
17 Feb, 2015 1 commit
- debugging larger frames write/read · 864a8593
  Andrey Filippov authored Feb 17, 2015
  
  864a8593
16 Feb, 2015 2 commits
- more debugging · 7c5ab53d
  Andrey Filippov authored Feb 16, 2015
  
  7c5ab53d
- modified scanline mode to work with SDRAM page crossing (by splitting in 2), debugging read mode · e3d5b404
  Andrey Filippov authored Feb 16, 2015
  
  e3d5b404
15 Feb, 2015 1 commit
- ran some tests with TEST_SCANLINE_WRITE, fixed some bugs · 547054f6
  Andrey Filippov authored Feb 15, 2015
  
  547054f6
14 Feb, 2015 1 commit
- debugging scanline read memory access · 8f79e6f7
  Andrey Filippov authored Feb 14, 2015
  
  8f79e6f7
13 Feb, 2015 3 commits
- split top level test fixture file into separate includes with tasks · cbbd4ed1
  Andrey Filippov authored Feb 13, 2015
  
  cbbd4ed1
- more debugging by simulation, bug fixing · 38d73a7b
  Andrey Filippov authored Feb 13, 2015
  
  38d73a7b
- debugging, more corrections, tested block write through PIO channel 1 · f4751492
  Andrey Filippov authored Feb 13, 2015
  
  f4751492
12 Feb, 2015 1 commit
- debugging, more corrections, tested write levelling/buffer reading · bb237119
  Andrey Filippov authored Feb 12, 2015
  
  bb237119
11 Feb, 2015 1 commit
- debugging/simulation · d899569e
  Andrey Filippov authored Feb 11, 2015
  
  d899569e
10 Feb, 2015 6 commits
- removed some old temporary files · 9acfc5c3
  Andrey Filippov authored Feb 10, 2015
  
  9acfc5c3
- moved directory phy under memcntrl (as it is a part of memory controller) · 466a4a4e
  Andrey Filippov authored Feb 10, 2015
  
  466a4a4e
- more simulation · dde1725e
  Andrey Filippov authored Feb 10, 2015
  
  dde1725e
- continue simulation, moved some code to includes after modifying VDT to... · f9e935af
  Andrey Filippov authored Feb 10, 2015
```
continue simulation, moved some code to includes after modifying VDT to support project-relative includes
```
  f9e935af
- Modified Veditor to search includes from project root in addition to relative to source file · ee2c4eef
  Andrey Filippov authored Feb 10, 2015
  
  ee2c4eef
- tested register writes, status generation, routing and reading · 9f629dc4
  Andrey Filippov authored Feb 10, 2015
  
  9f629dc4
09 Feb, 2015 1 commit
- started simulation · 99191719
  Andrey Filippov authored Feb 09, 2015
  
  99191719
08 Feb, 2015 1 commit
- Working on simulation testbench · 575da59a
  Andrey Filippov authored Feb 08, 2015
  
  575da59a
06 Feb, 2015 3 commits
- finalizing initial x393 and dependencies · 2d03240b
  Andrey Filippov authored Feb 06, 2015
  
  2d03240b
- editing x393.v · cd610a00
  Andrey Filippov authored Feb 06, 2015
  
  cd610a00
- finishing initial mcntrl393.v · dcc5752f
  Andrey Filippov authored Feb 06, 2015
  
  dcc5752f
05 Feb, 2015 1 commit
- modifying memory controller buffer interface · ecd4a509
  Andrey Filippov authored Feb 05, 2015
  
  ecd4a509
04 Feb, 2015 1 commit
- moved buffer adddress away from sequencer, continue ot memory controller top module · db31f7a9
  Andrey Filippov authored Feb 04, 2015
  
  db31f7a9
02 Feb, 2015 1 commit
- continue on mcntrl393, fixing some bugs too · e6cbe171
  Andrey Filippov authored Feb 02, 2015
  
  e6cbe171
01 Feb, 2015 2 commits
- started top module for memory controller with channle buffers, added cascaded status multiplexers · 94f77f4d
  Andrey Filippov authored Feb 01, 2015
  
  94f77f4d
- Added more code: Farme level scanline memory interface with window,... · 0adb43af
  Andrey Filippov authored Feb 01, 2015
```
Added more code: Farme level scanline memory interface with window, multiplexor for multiple channels sharing the same linear R/W command encoder
```
  0adb43af