next snapshot

    parameter MCONTR_PHY_16BIT_WBUF_DELAY =     'h2,    // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)

    parameter MCONTR_PHY_16BIT_EXTRA_REL =      'h3,    // 1 bit - set extra parameters (currently just inv_clk_div)

    parameter MCONTR_PHY_STATUS_CNTRL =         'h4,    // 8 bits - write to status control

0x1060..106f: arbiter priority data

    parameter MCONTR_ARBIT_ADDR =              'h060,   // Address to set channel priorities

    parameter MCONTR_ARBIT_ADDR_MASK =         'h3f0,   // Address mask to set channel priorities

// Status read address

    parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers

    parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers

module  ddr_refresh(

    input       rst,

    input       clk,

    input [7:0] refresh_period, // in 16*clk

    input [7:0] refresh_period, // in 16*clk, 0 - disable refresh, turn off requests

    input       set, // and reset counters

    output      want, // turns off next cycle after grant (or stays on if more are needed)

    output      need,

    output reg  want, // turns off next cycle after grant (or stays on if more are needed)

    output reg  need,

    input       grant // 1 cycle

);

    reg   [3:0] pre_div;

    reg         cry;

    wire        over=(period_cntr == 0) && cry;

    reg         refresh_due;

    assign want = pending_rq != 0;

    assign need = pending_rq[4:3] != 0;

    reg         en_refresh;

    always @ (posedge rst or posedge clk) begin

        if (rst)       en_refresh <= 0;

        else if (set)  en_refresh <= (refresh_period != 0);

        if (rst)                      pre_div <= 0;

        else if (set)  pre_div <= 0;

        else if (set || !en_refresh)  pre_div <= 0;

        else                          pre_div <= pre_div +1;

        if (rst)       cry <= 0;

        else if (set)  pending_rq <= 0;

        else if ( refresh_due && !grant) pending_rq <= pending_rq+1;

        else if (!refresh_due &&  grant) pending_rq <= pending_rq-1;

        if (rst) want <= 0;

        else     want<= en_refresh && (pending_rq != 0);

        if (rst) need <= 0;

        else     need <= en_refresh && (pending_rq[4:3] != 0);

    end

endmodule

    input             clk,

    input      [15:0] want_rq,   // both want_rq and need_rq should go inactive after being granted  

    input      [15:0] need_rq,

    input             en_sch,    // needs to be disabled before next access can be scheduled

    input             en_schedul,    // needs to be disabled before next access can be scheduled

    output            need,      // granted access is "needed" one, not just "wanted"

    output            grant,     // single-cycle granted channel access

    output      [3:0] grant_chn, // granted  channel number, valid with grant, stays valid until en_sch is deasserted

    output      [3:0] grant_chn, // granted  channel number, valid with grant, stays valid until en_schedul is deasserted

    // todo: add programming  sequencer address for software sequencer program? Or should it come from the channel?

    input       [3:0] pgm_addr,  // channel address to program priority

    input [width-1:0] pgm_data,  // priority data for the channel

    wire [3:0] index; // channel index to select

    wire index_valid; // selected index valid ("needed" or "wanted")

    reg grant_r;      // 1 cycle long

    reg grant_sent; // turns on after grant, until en_sch is de-asserted

    reg grant_sent; // turns on after grant, until en_schedul is de-asserted

    reg [3:0] grant_chn_r;

    wire grant_w;

//    assign event_w=new_want | new_need;

    assign next_need_conf=(need_conf &  need_rq) | need_set;

    assign grant=grant_r;

    assign grant_chn=grant_chn_r;

    assign grant_w=en_sch && index_valid && !grant_sent;

    assign grant_w=en_schedul && index_valid && !grant_sent;

    generate

        genvar i;

        for (i=0;i<16;i=i+1) begin: pri_reg_block

            grant_sent <=0;

            grant_chn_r <=0;

        end else begin

            grant_r    <= grant_w; // en_sch && index_valid && !grant_sent;

            grant_sent <= (grant_sent && en_sch) || grant_r;

            grant_r    <= grant_w; // en_schedul && index_valid && !grant_sent;

            grant_sent <= (grant_sent && en_schedul) || grant_r;

            if (grant_w) grant_chn_r <= index[3:0];   

        end

    end

        .NUM_CYCLES (4),

        .ADDR_WIDTH (3),

        .DATA_WIDTH (16)

    ) cmd_deser_0bit_i (

    ) cmd_deser_16bit_i (

        .rst        (rst), // input

        .clk        (mclk), // input

        .ad         (cmd_ad), // input[7:0]