Commit ea0f8823 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

fpga vesrsion 0xbc, added configuration for Eyesis

parent a13792e4

fpga_version.vh

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@@ -35,7 +35,8 @@ 
 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

        parameter FPGA_VERSION =          32'h039300bb;      //parallel, adding i2c almost full. -0.101/8, 79.37%

        parameter FPGA_VERSION =          32'h039300bc;      //parallel, 100kHz min i2c speed -0.076/8, 79.69%

//        parameter FPGA_VERSION =          32'h039300bb;      //parallel, adding i2c almost full. -0.101/8, 79.37%

//      parameter FPGA_VERSION =          32'h039300ba;      //parallel, fixing introduced by debug bug in sens_parallel12.v: met, 80.03%

//      parameter FPGA_VERSION =          32'h039300b9;      //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64%

//      parameter FPGA_VERSION =          32'h039300b8;      //parallel, working on camsync -0.330/99, 80.52% -> -0.143 /40, 79.88%

py393/hargs-after

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@@ -5,5 +5,4 @@ 
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle

-c bitstream_set_path /usr/local/verilog/x393_parallel.bit

-c specify_phys_memory

-c specify_window

-i

py393/hargs-eyesis

0 → 100644
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-d TARGET_MODE=1

-f /usr/local/verilog/system_defines.vh

-f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh

-l /usr/local/verilog/x393_cur_params_target.vh

-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle

-c bitstream_set_path /usr/local/verilog/x393_parallel.bit

-c setupEyesisPower 50 100

-c measure_all "*DI"

-c setSensorClock 24.0 "2V5_LVDS"

-c set_rtc

py393/x393_export_c.py

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@@ -1826,7 +1826,7 @@ class X393ExportC(object): 
        dw.append(("i2c_fifo_nempty",        8, 1,0,  "I2C read FIFO has data"))

        dw.append(("i2c_fifo_lsb",           9, 1,0,  "I2C FIFO byte counter (odd/even bytes)"))

        dw.append(("busy",                  10, 1,0,  "I2C sequencer busy"))

        dw.append(("wr_full",               11, 1,0,  "Write buffer almost full (14..3/4 in ASAP mode)"))

        dw.append(("wr_full",               11, 1,0,  "Write buffer almost full (1/4..3/4 in ASAP mode)"))

        dw.append(("frame_num",             12, 4,0,  "I2C sequencer frame number"))

        dw.append(("req_clr",               16, 1,0,  "Request for clearing fifo_wp (delay frame sync if previous is not yet sent out)"))

        dw.append(("reset_on",              17, 1,0,  "Reset in progress"))

py393/x393_jpeg.py

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@@ -1072,6 +1072,8 @@ camsync_setup 0xf # sensor mask - use local timestamps) 
jpeg_write  "img.jpeg" 0 80



####### Parallel - setup sensor 1 (sensor 0 is set by drivers) ##############

cd /usr/local/verilog/; test_mcntrl.py @hargs-after



setup_all_sensors True None 0x2 # sensor 1

set_sensor_io_ctl  1 None None 1 # Set ARO low - check if it is still needed?

#set quadrants
@@ -1099,6 +1101,8 @@ jpeg_write "img.jpeg" 1 80 




################## Parallel ##################

cd /usr/local/verilog/; test_mcntrl.py @hargs-after



cd /usr/local/verilog/; test_mcntrl.py @tpargs -x