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Commit e5bc283e authored Feb 09, 2018 by Oleg Dzhimiev

frequency and voltage for 14MPx

parent 19e6e962

py393/hargs-hispi

+1 −1

Original line number	Diff line number	Diff line
		@@ -6,5 +6,5 @@
		-c bitstream_set_path /usr/local/verilog/x393_hispi.bit
		-c setupSensorsPower "HISPI"
		-c measure_all "*DI"
		-c setSensorClock 24.0 "2V5_LVDS"
		-c setSensorClock 24.444 "1V8_LVDS"
		-c set_rtc

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