Commit e50c51b6 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

added default eclipse project settings

parent 1bdf877a

eclipse_settings/.project

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<?xml version="1.0" encoding="UTF-8"?>

<projectDescription>

	<name>x393</name>

	<comment></comment>

	<projects>

	</projects>

	<buildSpec>

		<buildCommand>

			<name>org.python.pydev.PyDevBuilder</name>

			<arguments>

			</arguments>

		</buildCommand>

	</buildSpec>

	<natures>

		<nature>com.elphel.vdt.veditor.HdlNature</nature>

		<nature>org.python.pydev.pythonNature</nature>

	</natures>

</projectDescription>

eclipse_settings/.project_dct

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<?xml version="1.0" encoding="UTF-8"?>

<projectDescription>

	<name>x393_dct</name>

	<comment></comment>

	<projects>

	</projects>

	<buildSpec>

		<buildCommand>

			<name>org.python.pydev.PyDevBuilder</name>

			<arguments>

			</arguments>

		</buildCommand>

	</buildSpec>

	<natures>

		<nature>com.elphel.vdt.veditor.HdlNature</nature>

		<nature>org.python.pydev.pythonNature</nature>

	</natures>

</projectDescription>

eclipse_settings/.settings/com.elphel.vdt.FPGA_project.prefs

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FPGA_project_@_DUTTopFile=cocotb/x393_dut.v

FPGA_project_@_DUTTopModule=x393_dut

FPGA_project_@_ImplementationTopFile=x393.v

FPGA_project_@_SimulationTopFile=x393_testbench03.tf

FPGA_project_@_SimulationTopModule=x393_testbench03

FPGA_project_@_part=xc7z030fbg484-2

com.elphel.store.context.FPGA_project=FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_part<-@\#\#@->FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->

com.elphel.store.version.FPGA_project=1.0

eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.FPGA_project_old.prefs

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FPGA_project_@_DUTTopFile=cocotb/x393_dut.v

FPGA_project_@_DUTTopModule=x393_dut

FPGA_project_@_ImplementationTopFile=x393.v

FPGA_project_@_SimulationTopFile=x393_testbench03.tf

FPGA_project_@_SimulationTopModule=x393_testbench03

FPGA_project_@_part=xc7z030fbg484-1

com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->

com.elphel.store.version.FPGA_project=1.0

eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.ISExst.prefs

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ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->

ISExst_@_constraints=ddrc_test01.xcf

com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->

eclipse.preferences.version=1