simulating/bug fixing

            2'h3: data2 <= { 6'b0,data1      };

            2'h3: data2 <= { 6'b0,data1      };

        endcase

        endcase

        if (stage[0]) case (dlen1[4:0])

        if (stage[0]) case (dlen1[4:0])

/*        

            5'h00: dmask2_rom <= 32'hffffffff;

            5'h01: dmask2_rom <= 32'hfffffffe;

            5'h02: dmask2_rom <= 32'hfffffffc;

            5'h03: dmask2_rom <= 32'hfffffff8;

            5'h04: dmask2_rom <= 32'hfffffff0;

            5'h05: dmask2_rom <= 32'hffffffe0;

            5'h06: dmask2_rom <= 32'hffffffc0;

            5'h07: dmask2_rom <= 32'hffffff80;

            5'h08: dmask2_rom <= 32'hffffff00;

            5'h09: dmask2_rom <= 32'hfffffe00;

            5'h0a: dmask2_rom <= 32'hfffffc00;

            5'h0b: dmask2_rom <= 32'hfffff800;

            5'h0c: dmask2_rom <= 32'hfffff000;

            5'h0d: dmask2_rom <= 32'hffffe000;

            5'h0e: dmask2_rom <= 32'hffffc000;

            5'h0f: dmask2_rom <= 32'hffff8000;

            5'h10: dmask2_rom <= 32'hffff0000;

            5'h11: dmask2_rom <= 32'hfffe0000;

            5'h12: dmask2_rom <= 32'hfffc0000;

            5'h13: dmask2_rom <= 32'hfff80000;

            5'h14: dmask2_rom <= 32'hfff00000;

            5'h15: dmask2_rom <= 32'hffe00000;

            5'h16: dmask2_rom <= 32'hffc00000;

            5'h17: dmask2_rom <= 32'hff800000;

            5'h18: dmask2_rom <= 32'hff000000;

            5'h19: dmask2_rom <= 32'hfe000000;

            5'h1a: dmask2_rom <= 32'hfc000000;

            5'h1b: dmask2_rom <= 32'hf8000000;

            5'h1c: dmask2_rom <= 32'hf0000000;

            5'h1d: dmask2_rom <= 32'he0000000;

            5'h1e: dmask2_rom <= 32'hc0000000;

            5'h1f: dmask2_rom <= 32'h80000000;

*/

            5'h00: dmask2_rom <= 32'hffffffff;

            5'h00: dmask2_rom <= 32'hffffffff;

            5'h01: dmask2_rom <= 32'h7fffffff;

            5'h01: dmask2_rom <= 32'h7fffffff;

            5'h02: dmask2_rom <= 32'h3fffffff;

            5'h02: dmask2_rom <= 32'h3fffffff;

    input             clk,

    input             clk,

    input             in_valid,

    input             in_valid,

    input      [15:0] huff_code,

    input      [15:0] huff_code,

    input      [ 3:0] huff_code_len,

    input      [ 3:0] huff_code_len, // 0 means 16

    input      [10:0] literal,

    input      [10:0] literal,

    input      [ 3:0] literal_len,

    input      [ 3:0] literal_len,

    output reg        out_valid, // latency 5 from input

    output reg        out_valid, // latency 5 from input

    reg         [4:0] olen3;

    reg         [4:0] olen3;

    reg         [3:0] hlen0;

    reg         [3:0] hlen0;

    reg         [3:0] hlen1;

    reg         [3:0] hlen1;

    reg         [3:0] hlen2;

    reg         [4:0] hlen2;

    reg         [3:0] hlen2m1;

    reg         [3:0] hlen2m1;

    reg         [1:0] hlen3m1;

    reg         [1:0] hlen3m1;

    reg         [3:0] valid;

    reg         [3:0] valid;

        endcase

        endcase

        llen2 <= llen1;

        llen2 <= llen1;

        huff2 <= huff1;

        huff2 <= huff1;

        hlen2 <= hlen1;

        hlen2 <= {~(|hlen1),hlen1};

        hlen2m1 <= hlen1 - 1; // s0 

        hlen2m1 <= hlen1 - 1; // s0 

        valid[2] <= valid[1];

        valid[2] <= valid[1];

        // layer 3

        // layer 3

[*]

[*]

[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI

[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI

[*] Tue Oct 27 05:53:02 2015

[*] Tue Oct 27 07:42:39 2015

[*]

[*]

[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151026231135006.fst"

[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151026231135006.fst"

[dumpfile_mtime] "Tue Oct 27 05:52:50 2015"

[dumpfile_mtime] "Tue Oct 27 05:52:50 2015"

[dumpfile_size] 257666662

[dumpfile_size] 257666662

[savefile] "/home/andrey/git/x393/x393_testbench03.sav"

[savefile] "/home/andrey/git/x393/x393_testbench03.sav"

[timestart] 147990400

[timestart] 147873900

[size] 1823 1180

[size] 1823 1180

[pos] 1920 0

[pos] 1920 0

*-15.037372 148077500 108390000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-16.209452 148132600 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] x393_testbench03.

[treeopen] x393_testbench03.

[treeopen] x393_testbench03.par12_hispi_psp4l0_i.

[treeopen] x393_testbench03.par12_hispi_psp4l0_i.

[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].

[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].

[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.

[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.

[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.

[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.

[sst_width] 340

[sst_width] 340

[signals_width] 404

[signals_width] 342

[sst_expanded] 1

[sst_expanded] 1

[sst_vpaned_height] 514

[sst_vpaned_height] 514

@820

@820

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotEOB

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotEOB

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastBlock

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastBlock

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastWord

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastWord

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ready_to_flush

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.typeDC

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.typeDC

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.typeAC

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.typeAC

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tbsel_YC0

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tbsel_YC0

@22

@22

[color] 2

[color] 2

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.q[15:0]

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.q[15:0]

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.imgsz32[19:0]

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.etrax_dma[3:0]

@28

@28

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_time_out

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_time_out

@22

@22

@28

@28

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8h

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8h

@29

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8l

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8l

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.running

@1000200

@1000200

-stuffer

-stuffer

@800200

@800200

-

-

@1000200

@1000200

-huffman_singleclk

-huffman_singleclk

@c00200

@800200

-stuffer32

-stuffer32

@28

@28

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds

-group_end

-group_end

@200

@200

-

-

@1401200

@1000200

-stuffer32

-stuffer32

@800200

@800200

-new_compressor

-new_compressor

@22

@22

[color] 2

[color] 2

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.data_out[31:0]

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.data_out[31:0]

@28

@29

[color] 2

[color] 2

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.data_out_valid

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.data_out_valid

@28

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.done

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.done

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.running

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.running

@22

x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]

@200

@200

-

-

@1000200

@1000200